Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

Abstract: Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measured in response to the high-temperature thermal condition. Operation of the NAND device may then be modified based on the workload and the high-temperature thermal condition.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a reflow-protection mode, and to transition from the reflow-protection mode to a normal-operation mode after the initial data exceeds the threshold amount.

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).

Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

Abstract: Disclosed in some examples are methods, systems, machine-readable mediums, and NAND devices which create logical partitions when requested to create a physical partition. The controller on the NAND mimics the creation of the physical partition to the host device that requested the physical partition. Thus, the host device sees the logical partition as a physical partition. Despite this, the NAND does not incur the memory storage expense of creating a separate partition, and additionally the NAND can borrow cells for overprovisioning from another partition. In these examples, a host device operating system believes that a physical partition has been created, but the NAND manages the memory as a contiguous pool of resources. Thus, a logical partition is created at the NAND memory controller level—as opposed to at the operating system level.

Abstract: Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measured in response to the high-temperature thermal condition. Operation of the NAND device may then be modified based on the workload and the high-temperature thermal condition.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

Abstract: Devices and techniques for random access memory power savings are disclosed herein. Data contained in RAM is compressed in response to obtaining a trigger. Here, the RAM organized into several discrete hardware components with a corresponding power control. The data contained in the RAM is replaced with the compressed data to free a discrete hardware component of the RAM. The discrete hardware component is then powered down via the corresponding power control.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

Abstract: Devices and techniques for efficient allocation of storage connection resources are disclosed herein. An active trigger for a storage device is received when the storage device is in an idle state. A workload that corresponds to the storage device is measured to determine that the workload meets a threshold. Connection parameters, for a connection to the storage device, are negotiated based on the workload in response to receipt of the active trigger and the workload meeting the threshold. The workload is then executed on the storage device via the connection using the connection parameters.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a reflow-protection mode, and to transition from the reflow-protection mode to a normal-operation mode after the initial data exceeds the threshold amount.