Patents by Inventor Sebastien Cremer

Sebastien Cremer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10877211
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Publication number: 20200116927
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Application
    Filed: November 26, 2019
    Publication date: April 16, 2020
    Inventors: Alain Chantre, Sébastien Cremer
  • Patent number: 10511147
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 17, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • Patent number: 10488587
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 26, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Publication number: 20190280144
    Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
  • Publication number: 20190280146
    Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
  • Patent number: 10359652
    Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 23, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Charles Baudot, Maurin Douix, Frederic Boeuf, Sébastien Cremer
  • Patent number: 10139563
    Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 27, 2018
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Charles Baudot, Alain Chantre, Sébastien Cremer
  • Publication number: 20180278021
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • Patent number: 10014660
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 3, 2018
    Assignees: Commisariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • Publication number: 20180136496
    Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Charles Baudot, Maurin Douix, Frederic Boeuf, Sébastien Cremer
  • Patent number: 9899800
    Abstract: A III-V heterostructure laser device located in and/or on silicon, including a III-V heterostructure gain medium, a rib optical waveguide, located facing the gain medium and including a strip waveguide equipped with a longitudinal rib, the rib optical waveguide being located in the silicon, two sets (RBE-A, RBE-B) of Bragg gratings formed in the rib optical waveguide and located on either side of the III-V heterostructure gain medium, each set (RBE-A, RBE-B) of Bragg gratings including a first Bragg grating (RB1-A, RB1B) having a first pitch and formed in the rib and a second Bragg grating (RB2-A, RB2-B) having a second pitch different from the first pitch and formed on that side of the rib waveguide which is opposite the rib.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: February 20, 2018
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, ST Microelectronics SA, ST Microelectronics (Crolles 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez
  • Patent number: 9891450
    Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles Baudot, Maurin Douix, Frédéric Boeuf, Sébastien Cremer
  • Publication number: 20170371099
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Inventors: Alain Chantre, Sébastien Cremer
  • Publication number: 20170192170
    Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Charles BAUDOT, Alain CHANTRE, Sébastien CREMER
  • Publication number: 20170141541
    Abstract: A III-V heterostructure laser device located in and/or on silicon, including a III-V heterostructure gain medium, a rib optical waveguide, located facing the gain medium and including a strip waveguide equipped with a longitudinal rib, the rib optical waveguide being located in the silicon, two sets (RBE-A, RBE-B) of Bragg gratings formed in the rib optical waveguide and located on either side of the III-V heterostructure gain medium, each set (RBE-A, RBE-B) of Bragg gratings including a first Bragg grating (RB1-A, RB1B) having a first pitch and formed in the rib and a second Bragg grating (RB2-A, RB2-B) having a second pitch different from the first pitch and formed on that side of the rib waveguide which is opposite the rib.
    Type: Application
    Filed: November 11, 2016
    Publication date: May 18, 2017
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, ST Microelectronics SA, ST Microelectronics (Crolles 2) SAS
    Inventors: Thomas FERROTTI, Badhise BEN BAKIR, Alain CHANTRE, Sebastien CREMER, Helene DUPREZ
  • Publication number: 20170075148
    Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
    Type: Application
    Filed: March 30, 2016
    Publication date: March 16, 2017
    Inventors: Charles BAUDOT, Maurin DOUIX, Frédéric BOEUF, Sébastien CREMER
  • Patent number: 9507089
    Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: November 29, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Patent number: 9461441
    Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: October 4, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2 ) SAS
    Inventors: Alain Chantre, Charles Baudot, Sébastien Cremer
  • Publication number: 20160233641
    Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.
    Type: Application
    Filed: November 19, 2015
    Publication date: August 11, 2016
    Inventors: Alain CHANTRE, Charles BAUDOT, Sébastien CREMER