Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.

Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Abstract: An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line.

Abstract: A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.

Abstract: An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line.

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.

Abstract: A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.

Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

Abstract: A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.

Abstract: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.

Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.

Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Abstract: A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

Abstract: An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.

Abstract: A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.