Abstract: A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-sate memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.

Abstract: A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.

Abstract: A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals.

Abstract: A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material.

Abstract: An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

Abstract: The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.

Abstract: Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die.

Abstract: A controller including a switch, a first module, a second module, and a control module. The switch receives current from an inductor and bypasses a portion of the current from being received by a load. The switch is cycled between a first state and a second state at a frequency. The first module, for a first cycle of the switch, determines a first amount of time the switch is in the first state. The second module, based on the first amount of time, determines a second amount of time for a level of the current to decrease to a predetermined level. The second amount of time begins during the first cycle and when the switch transitions from the first state to the second state. The control module, based on the second amount of time and prior to the current decreasing to the predetermined level, changes the frequency of the switch.

Abstract: A differential power amplifier including a push-pull pair of transistors, a capacitance, a first inductance, and a second inductance. The push-pull pair of transistors includes first and second transistors. The first transistor includes control and output terminals. The second transistor includes input and control terminals. The control terminals of the first and second transistors collectively receive a differential input signal. The output and input terminals collectively provide a differential output signal. The capacitance is connected to the output and input terminals. The first capacitance cancels first harmonics at the output terminal of the first transistor with second harmonics at the input terminal of the second transistor. The first transistor and the first inductance are connected in series between a voltage source and a reference terminal. The second transistor and the second inductance are connected in series between the voltage source and the reference terminal.

Abstract: A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.

Abstract: A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.

Abstract: A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module.

Abstract: A monitoring module monitors a charge level of a battery in a vehicle. A network interface module transmits a first set of charging parameters for charging the battery to a utility company and receives a reply and a charge return request from the utility company for returning charge from the battery to the utility company. The first set of charging parameters includes the charge level of the battery and a first time of the day for charging the battery. The reply includes a second time of the day for charging the battery. A control module generates a first signal based on the reply and the first set of charging parameters, and a second signal based on the charge return request and charge return parameters. A charging module charges the battery based on the first signal. A charge retrieval module returns the charge based on the second signal.

Abstract: A system on a chip includes a semiconductor memory, a memory control module, a non-volatile memory and a memory decoder module. The semiconductor memory has i) first memory locations, and ii) second memory locations. Each of the second memory locations is redundant to one of the first memory locations. The memory control module is configured to detect defective ones of the first memory locations. The non-volatile memory has a memory repair database. The memory repair database is configured to store information associating respective addresses of the defective ones of the first memory locations with one or more of the second memory locations. The memory decoder module is configured to, based on the information stored in the memory repair database, respectively remap the respective addresses of the defective ones of the first memory locations to the one or more of the second memory locations.

Abstract: A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM.

Abstract: A system includes first, second, and third sets of LEDs and a control module. The first set of LEDs outputs light having wavelengths in a wavelength range in a spectrum of ultraviolet light and is coated with a phosphor to convert the ultraviolet light to blue light having wavelengths in a wavelength range in a spectrum of blue light. The second and third sets of LEDs output light having wavelengths in a wavelength range in the spectrum of blue light and is coated with phosphors to convert the blue light to light having wavelengths in a wavelength range in a spectrum of green, yellow, and red light. The second set of LEDs generates less red light than green light. The third set of LEDs generates less green light than red light. The current control module controls currents through the first, second, and third sets of LEDs to generate white light.

Abstract: A system including a base portion, which includes first and second sets of light emitting diodes (LEDs) to emit blue light having first and second wavelengths in first and second wavelength ranges in a spectrum of blue light, a glass layer arranged at a second predetermined distance from the base portion, and a plurality of coatings of first and second phosphors having a predetermined length arranged in an alternating pattern on a surface of the glass layer facing toward the LEDs. The LEDs of the first and second sets are arranged on the base portion in an alternating pattern and are separated from each other by a first predetermined distance. Centers of the coatings of the first and second phosphors respectively align with centers of corresponding LEDs in the first and second sets.

Abstract: A lamp including a first set of light emitting diodes configured to generate first light, a second set of light emitting diodes configured to generate second light, and a third set of light emitting diodes configured to generate third light. The first light, the second light, and the third light combine to produce white light. A first switch is located at a base portion of the lamp. The state of the first switch corresponds to a color temperature of the white light. A color temperature adjustment module is configured to vary outputs of the first, second, and third sets of light emitting diodes in accordance with the color temperature of the white light selected by a user using the first switch.

Abstract: A system including a first set of light emitting diodes, a second set of light emitting diodes, and a control module. The first set of light emitting diodes is configured to emit blue light having first wavelengths in a first wavelength range in a spectrum of blue light. The first set of light emitting diodes includes a green phosphor configured to convert the blue light having the first wavelengths to green light. The second set of light emitting diodes is configured to emit blue light having second wavelengths in a second wavelength range in the spectrum of blue light. The second set of light emitting diodes includes a red phosphor configured to convert the blue light having the second wavelengths to red light. The first wavelength range is less than the second wavelength range. The control module is configured to control currents through the first set of light emitting diodes and the second set of light emitting diodes.

Abstract: A receiver including a mixer configured to generate (i) a first output and (ii) a second output, a first capacitance coupled to the first output, and a second capacitance coupled to the second output, A controller is configured to program (i) the first capacitance and (ii) the second capacitance to a first capacitance value in response to operating the receiver in a first mode, and program (i) the first capacitance and (ii) the second capacitance to a second capacitance value in response to operating the receiver in a second mode. The first capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the first mode. The second capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the second mode.