Patents by Inventor Sehat Sutardja

Sehat Sutardja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8970185
    Abstract: A switching regulator includes a high-side driver configured to receive an input voltage, and a low-side driver configured to receive the input voltage. The high-side driver and the low-side driver are configured to provide an output voltage based on the input voltage. A charge pump module is configured to receive a supply voltage that varies between a first voltage level and a second voltage level greater than the first voltage level, generate the input voltage based on the supply voltage, and maintain the input voltage at the second voltage level independent of variations in the supply voltage.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: March 3, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Sofjan Goenawan, Gareth Seng Thai Yeo
  • Patent number: 8970101
    Abstract: A system including a base portion, which includes first and second sets of light emitting diodes (LEDs) to emit blue light having first and second wavelengths in first and second wavelength ranges in a spectrum of blue light, a glass layer arranged at a second predetermined distance from the base portion, and a plurality of coatings of first and second phosphors having a predetermined length arranged in an alternating pattern on a surface of the glass layer facing toward the LEDs. The LEDs of the first and second sets are arranged on the base portion in an alternating pattern and are separated from each other by a first predetermined distance. Centers of the coatings of the first and second phosphors respectively align with centers of corresponding LEDs in the first and second sets.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: March 3, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Publication number: 20150035160
    Abstract: Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.
    Type: Application
    Filed: October 10, 2014
    Publication date: February 5, 2015
    Inventors: Sehat Sutardja, Shiann-Ming Liou, Huahung Kao
  • Patent number: 8947013
    Abstract: A lamp including a first set of light emitting diodes configured to generate first light, a second set of light emitting diodes configured to generate second light, and a third set of light emitting diodes configured to generate third light. The first light, the second light, and the third light combine to produce white light. A first switch is located at a base portion of the lamp. The state of the first switch corresponds to a color temperature of the white light. A color temperature adjustment module is configured to vary outputs of the first, second, and third sets of light emitting diodes in accordance with the color temperature of the white light selected by a user using the first switch.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: February 3, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Patent number: 8946890
    Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: February 3, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Chung Chyung Han, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu
  • Patent number: 8941529
    Abstract: A circuit including an amplifier. The circuit includes N capacitances that include first ends and second ends. The first ends communicate with an input of the amplifier. A first switch is configured to selectively connect the input of the amplifier to a reference potential during a first phase. N switches are configured to connect each of the second ends of the N capacitances to a voltage input, the reference potential and a voltage reference and selectively connect each of the second ends of the N capacitances to one of a voltage input, the reference potential and a voltage reference during a second phase. The first and second phases are non-overlapping.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: January 27, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20150022117
    Abstract: A system including a plurality of switches and a comparator. The plurality of switches is configured to respectively supply a plurality of currents via respective terminals to a plurality of sets of light emitting diodes. The sets of light emitting diodes are configured to respectively output light having wavelengths in a plurality of wavelength ranges in a spectrum of blue light. The comparator is configured to compare a reference voltage to a voltage at one of the terminals of one of the plurality of switches connected to one of the sets of light emitting diodes, and to adjust, based on the comparison, biasing of the plurality of switches to maintain a predetermined ratio of the plurality of currents.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Publication number: 20150024590
    Abstract: Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 22, 2015
    Inventor: Sehat Sutardja
  • Patent number: 8937511
    Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: January 20, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Pantas Sutardja, Sehat Sutardja
  • Patent number: 8937435
    Abstract: Aspects of the disclosure provide a circuit that includes a first circuit, a second circuit and a bridge circuit. The first circuit is coupled to a magnetic component to receive electric energy transferred via the magnetic component and thus configured to store the electric energy and generate a supply voltage. The second circuit is also coupled to the magnetic component. The second circuit is switchable and is configured to deplete a portion of the electric energy when the second circuit is switched on. The bridge circuit is coupled between the first circuit and the second circuit to provide a charge flow path when the second circuit is switched off.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: January 20, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Wanfeng Zhang
  • Patent number: 8937457
    Abstract: A system including a plurality of cells connected in series in a rechargeable battery pack and a plurality of cell balancing modules. Each cell balancing module performs voltage balancing of a respective pair of cells. Each cell balancing module includes a communication module to (i) transmit, via a communication link, information about voltages of the respective pair of cells to an adjacent cell balancing module and (ii) receive, via the communication link, from the adjacent cell balancing module, information about voltages of cells corresponding to the adjacent cell balancing module. Each cell balancing module performs, based on the information received from the adjacent cell balancing module, the voltage balancing in response to a voltage difference between any of the plurality of cells being greater than or equal to a predetermined threshold instead of performing the voltage balancing based on a difference between voltages of the respective pair of cells.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: January 20, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja
  • Publication number: 20150015158
    Abstract: A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode.
    Type: Application
    Filed: September 29, 2014
    Publication date: January 15, 2015
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang, Jinho Choi
  • Patent number: 8935464
    Abstract: A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-state memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: January 13, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Po-Chien Chang, Roawen Chen
  • Patent number: 8901648
    Abstract: Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: December 2, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Publication number: 20140347894
    Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: MARVELL WORLD TRADE LTD
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang
  • Patent number: 8896387
    Abstract: In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 25, 2014
    Assignee: Marvell International Ltd.
    Inventors: Alessandro Venca, Enrico Sacchi, Sehat Sutardja
  • Publication number: 20140334201
    Abstract: A system including a converter and a snubber circuit. The converter converts an alternating current voltage into a direct current voltage and outputs the direct current voltage across an inductance and a switch connected in series. The inductance has a center tap connected to a node, which is connected to a load. In response to the switch being turned on, a first current flows through the inductance and the switch. In response to the switch being turned off, a second current flows from the node to the load. The snubber circuit is connected across the node and a junction of the inductance and the switch. In response to the switch being turned off, the snubber circuit receives a third current from the junction, and supplies a first portion of the third current to the node. The second current and the first portion of the third current flow through the load.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 13, 2014
    Applicant: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8880017
    Abstract: A system includes a transceiver configured to receive a composite signal. The composite signal is a composite of a transmit signal and a receive signal. A replica transmitter is configured to generate a replica transmit signal based on the transmit signal. A transmit canceller is configured to recover the receive signal at least in part by resistively summing the composite signal and the replica transmit signal.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: November 4, 2014
    Assignee: Marvell International Ltd.
    Inventors: Pierte Roo, Sehat Sutardja
  • Publication number: 20140325132
    Abstract: A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 30, 2014
    Inventors: Sehat Sutardja, Son Hong Ho
  • Patent number: 8874948
    Abstract: A device includes a first processor and a second processor. The first processor is configured to operate in accordance with a first power mode. The first processor includes a first transistor. The first processor is configured to, while operating in accordance with the first power mode, switch the first transistor at a first duty cycle. The second processor is configured to operate in accordance with a second power mode. The second processor includes a second transistor. The second processor is configured to, while operating in accordance with the second power mode, switch the second transistor at a second duty cycle. The second duty cycle is greater than the first duty cycle. The second processor consumes less power while operating in accordance with the second power mode than the first processor consumes while operating in accordance with the first power mode.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: October 28, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Hong-Yi Chen