Patents by Inventor Sehat Sutardja

Sehat Sutardja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150364418
    Abstract: A circuit including: a die a first substrate and at least one active device; an integrated passive device including a first layer, a second substrate, a second layer and an inductance; and a third layer. The inductance includes vias and is an electrostatic discharge inductance. The vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars. The pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.
    Type: Application
    Filed: August 25, 2015
    Publication date: December 17, 2015
    Inventors: Poh Boon Leong, Hou Xian Loo, Sehat Sutardja, Wei Ding, Huy Thong Nguyen, Xiaowei Zhong
  • Publication number: 20150349732
    Abstract: A system includes a first amplifier stage and a second amplifier stage. The first amplifier stage is configured to amplify an input signal and generate first output signals. The first amplifier stage includes a common-source differential amplifier. The common-source differential amplifier includes a plurality of metal-oxide semiconductor field-effect transistors (MOSFETs) having source terminals connected to a common potential. The second amplifier stage includes a first differential amplifier and a second differential amplifier configured to respectively generate first and second differential outputs based on the first output signals. Each of the first and second differential amplifiers includes a plurality of MOSFETs having source terminals connected to the common potential via a respective balun.
    Type: Application
    Filed: May 21, 2015
    Publication date: December 3, 2015
    Inventors: Poh Boon Leong, Sehat Sutardja
  • Patent number: 9197434
    Abstract: A system for delivering content to a network device comprises a content requesting interface that allows a user to select desired content from available content. A queue stores identifiers of the desired selected content. A remote content provider is located remote from the network device, communicates with the queue and transmits the desired selected content to the network device based on a sequence of the identifiers of the desired selected content stored in the queue and on at least one of usage and storage status data associated with received selected content stored on the network device. The storage status data includes at least one of a hidden status, an erased status, and an amount of the received selected content stored in the memory.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: November 24, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9190952
    Abstract: A circuit including a tank circuit, a pair of transistors, a bias circuit, and a capacitor. The transistors include (i) drain terminals coupled to the tank circuit, (ii) source terminals coupled to each other, and (iii) gate terminals cross-coupled to the drain terminals via a pair of capacitors. The bias circuit is coupled to the gates of the pair of transistors to i) alternatingly turn on the pair of transistors during a plurality of peaks of an oscillating signal of the tank circuit, and ii) turn off the pair of transistors during a plurality of crossing points of the oscillating signal. The capacitor is coupled to (i) the tank circuit and (ii) the pair of transistors.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: November 17, 2015
    Assignee: Marvell International LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9187005
    Abstract: A monitoring module monitors a charge level of a battery in a vehicle. A network interface module transmits a first set of charging parameters for charging the battery to a utility company and receives a reply and a charge return request from the utility company for returning charge from the battery to the utility company. The first set of charging parameters includes the charge level of the battery and a first time of the day for charging the battery. The reply includes a second time of the day for charging the battery. A control module generates a first signal based on the reply and the first set of charging parameters, and a second signal based on the charge return request and charge return parameters. A charging module charges the battery based on the first signal. A charge retrieval module returns the charge based on the second signal.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 17, 2015
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9185755
    Abstract: A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang
  • Patent number: 9182915
    Abstract: A data access system including a processor having (i) one or more levels of cache, and (ii) a storage system that includes a main memory and a cache module. The cache module includes a controller and a final level of cache to be accessed by the controller prior to accessing the main memory. In response to data required by the processor not being cached within the one or more levels of cache of the processor, the processor generates an address of a physical location within the storage system. The controller converts the address of the physical location within the storage system into an address of a virtual location within the final level of cache. The address of the virtual location is useable by the cache module to determine whether the data required by the processor is cached within the final level of cache.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: November 10, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20150318022
    Abstract: A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.
    Type: Application
    Filed: May 1, 2015
    Publication date: November 5, 2015
    Inventor: Sehat Sutardja
  • Patent number: 9166632
    Abstract: A receiver including a mixer, a clock generator, a plurality of capacitances, a plurality of resistances, and a controller. The mixer includes a plurality of switches. The clock generator is configured to generate clock signals to drive the plurality of switches of the mixer. The plurality of capacitances couples the clock signals to respective inputs of the plurality of switches. The plurality of resistances couples to the respective inputs of the plurality of switches. The controller is configured to output a first signal to the plurality of resistances. The first signal determines one or more attributes of the clock signals. One or more switching characteristics of the plurality of switches of the mixer are based on the one or more attributes of the clock signals.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 20, 2015
    Assignee: Marvell International LTD.
    Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
  • Patent number: 9159691
    Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 13, 2015
    Assignee: Marvell World Trade LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9158355
    Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 13, 2015
    Assignee: Marvell World Trade LTD.
    Inventors: Sehat Sutardja, Hong-Yi Chen, Premanand Sakarda, Mark N. Fullerton, Jay Heeb
  • Patent number: 9158620
    Abstract: A memory module including a first memory, a second memory, a test module, and a control module. The first memory is configured to store pages of data to be tested for errors. The second memory is configured to store addresses for the pages of data and store copies of the pages of data. The test module is configured to perform testing on the pages of data stored in the first memory. The control module is configured to, prior to the testing being performed by the test module on the pages of data stored in the first memory, cause the second memory to store the addresses and the copies of the pages of data stored in the first memory and, subsequent to the testing being performed by the test module, store the copies of the pages of data to the first memory based on the addresses stored in the second memory.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: October 13, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Saeed Azimi
  • Publication number: 20150289360
    Abstract: A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.
    Type: Application
    Filed: February 20, 2015
    Publication date: October 8, 2015
    Inventors: Poh Boon Leong, Hou Xian Loo, Sehat Sutardja, Wei Ding, Huy Thong Nguyen
  • Publication number: 20150271889
    Abstract: A system includes first, second, and third sets of LEDs. The first set of LEDs generates ultraviolet light and converts the ultraviolet light to blue light using a phosphor coated on the first set of LEDs. The second and third sets of LEDs generate blue light and convert the blue light to green, yellow, and red light using phosphors coated on the second and third sets of LEDs. The second set of LEDs outputs less red light than green light. The third set of LEDs outputs less green light than red light. A combination of the blue, green, yellow, and red light output by the first, second, and third sets of LEDs produces white light.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Sehat Sutardja, Ravishanker Krishnamoorthy
  • Patent number: 9143083
    Abstract: A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 22, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Sehat Sutardja
  • Patent number: 9141619
    Abstract: A media player/recorder includes a wireless receiver to receive a signal representing media data, a storage device to store the media data, a storage controller to retrieve the media data from the storage device, and an output circuit to output the media data. The storage device stores a list of identifiers of desired media selections. The wireless receiver receives a signal representing an identifier of an offered media selection. The storage device stores the offered media selection when the identifier of the offered media selection corresponds to the identifier of one of the desired media selections.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: September 22, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Sehat Sutardja, Peter Loc, Hedley Rainnie, Eric B. Janofsky
  • Patent number: 9144137
    Abstract: A controller for a buck regulator for a lighting system including light emitting diodes includes a voltage control loop configured to compare a voltage reference and a feedback voltage. The feedback voltage is based upon a DC supply voltage to the controller. A voltage regulator is configured to receive an output of the voltage control loop and to generate a current reference. A current control loop is configured to receive a feedback current and to compare the current reference to the feedback current. A current regulator is configured to receive an output of the current control loop. A pulse width modulation circuit is configured to receive an output of the current regulator and to generate drive signals for first and second switches of the buck regulator.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: September 22, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja, Wanfeng Zhang
  • Patent number: 9137864
    Abstract: Aspects of the disclosure provide light emitting diode (LED) lighting devices, and methods to drive the LED lighting devices. An LED lighting device includes a transformer having a primary winding on a receiving path to receive electric energy from an energy source and a secondary winding on a driving path. A terminal of the receiving path and a terminal of the driving path have a same voltage level, such as ground. Further, the LED lighting device includes a primary switch configured to switch on the receiving path to receive and store the electric energy in the transformer, and to switch off the receiving path to allow the driving path to deliver the stored electric energy. The LED lighting device also includes an LED array coupled to the driving path to emit light in response to the delivered electric energy.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 15, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20150244410
    Abstract: A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.
    Type: Application
    Filed: February 20, 2015
    Publication date: August 27, 2015
    Inventors: Poh Boon Leong, Albert Wu, Long-Ching Wang, Sehat Sutardja
  • Publication number: 20150242137
    Abstract: A data access system including a processor having (i) one or more levels of cache, and (ii) a storage system that includes a main memory and a cache module. The cache module includes a controller and a final level of cache to be accessed by the controller prior to accessing the main memory. In response to data required by the processor not being cached within the one or more levels of cache of the processor, the processor generates an address of a physical location within the storage system. The controller converts the address of the physical location within the storage system into an address of a virtual location within the final level of cache. The address of the virtual location is useable by the cache module to determine whether the data required by the processor is cached within the final level of cache.
    Type: Application
    Filed: May 13, 2015
    Publication date: August 27, 2015
    Inventor: Sehat Sutardja