Abstract: In a polishing apparatus having a cover body with fluid pressing mechanism, during polishing, vibration and migration of sticking portion between a retainer and a membrane generated in downstream of rotation of a polishing platen is prevented by reducing sticking force between the retainer and the membrane to less than force needed to wafer polishing with rotation of the cover body.

Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

Abstract: The present invention provides a technique to reduce and suppress scratches and delamination, to suppress and control the development of dishing and erosion, and to polish at high polishing rate. Polishing is performed using a polishing solution, which contains an oxidizer, phosphoric acid, organic acid, a chemical to form inhibition layer, and water.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items, such as slurries and polishing pads, is reduced. A metal film formed on an insulating film having a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Abstract: In order to resolve problems of an increase in cost of transportation and vessels for polishing solutions to polish metal films, and of aging change of the polishing solutions, apparatus for preparing and mixing solutions of polishing materials without including abrasive are installed at a site the same as a site of polishing apparatus, an abrasive free slurry is supplied to the polishing apparatus and a metal film on a wiring substrate is polished to thereby form embedded metal wirings by which the cost of polishing metal can significantly be reduced and stability of the polishing solution is promoted.

Abstract: A polishing method comprising mechanically polishing the surface of a metal film by the use of a polishing solution comprising an oxidizer, a substance which renders an oxide water-soluble, a thickener and water, is suitable for polishing the metal film at a high removal rate with suppressed scratching, delamination, dishing and erosion, and can be applied to production of semiconductors, etc.

Abstract: The present invention provides a technique to reduce and suppress scratches and delamination, to suppress and control the development of dishing and erosion, and to polish at high polishing rate. Polishing is performed using a polishing solution, which contains an oxidizer, phosphoric acid, organic acid, a chemical to form inhibition layer, and water.

Abstract: The invention provides a method for manufacturing a semiconductor device with reduced dishing and erosion. In this method for manufacturing a semiconductor device, the convex/concave pattern is planarized by relatively moving a substrate having the convex/concave pattern on the surface and a polishing tool with pressing the convex/concave surface of the substrate on the polishing tool. The polishing tool is provided with a grindstone 10 having a plurality of polygonal segments 20, which comprises abrasive 23 that is bonded together with resin 24 and contains pores 22. The polygonal segments are arranged so that corners of three or more polygonal segments are not located near each other.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: A superfine electronic device is disclosed, which is constructed by atomic fine lines having a structure in which a plurality of atoms are arranged on one or a plurality of straight lines, in a ring shape or on curves with a size of atomic level, and which includes elements for doping electrons and holes. Using these atomic fine lines, it is possible to integrate semiconductor elements utilizing pn junctions at an atomic level with a high density. A groove having a sufficiently small size is formed in an insulating film disposed on a substrate. Then, atoms or molecules are supplied on the substrate and in the groove, which and are heated to a temperature sufficiently high for moving the atoms or molecules during or after the supply thereof to form a quantum fine line at edge portions of the groove.

Abstract: Problematic dishing and erosion in forming embedded metal interconnection by a chemical mechanical polishing (CMP) method are suppressed. Formation of embedded Cu interconnects 46a to 46e by chemical mechanical polishing of a Cu film 46 formed in interconnect trenches 40 to 44 is performed by abrasive-grain-free chemical mechanical polishing using a polishing liquid of an abrasive grain content less than 0.5 wt % (CMP of the first step); with-abrasive-grain chemical mechanical polishing using a polishing liquid of an abrasive grain content of 0.5 or more wt % (CMP of the second step); and selective chemical mechanical polishing using a polishing liquid to which an anticorrosive such as benzotriazole (BTA) is added (CMP of the third step).

Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: An apparatus comprising a fixed abrasive tool in which fine abrasive grains are uniformly dispersed and fixed, supply systems for processing liquids each containing an oxidizing agent, an organic acid, an inhibitor and purified water, and a sizing dresser capable of dressing the surface of the fixed abrasive tool at a constant size, and adapted to flow a processing liquid for polishing copper at a higher speed in the initial stage of processing, change the polishing liquid to another polishing liquid capable of polishing copper and barrier film substantially at an identical speed just before or just after the exposure of the barrier film and conduct conditioning during processing by driving the sizing dresser, the polishing method and the polishing apparatus enabling to decrease the cost in the existent CMP for planarization of copper wirings requiring two or more steps of CMP, as well as enabling to reduce dishing or erosion resulting in recesses for the wiring shape after planarization, which decrease the s

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

Abstract: The present invention provides a technique to reduce and suppress scratches and delamination, to suppress and control the development of dishing and erosion, and to polish at high polishing rate. Polishing is performed using a polishing solution, which contains an oxidizer, phosphoric acid, organic acid, a chemical to form inhibition layer, and water.