Patents by Inventor Seiji Nagahara

Seiji Nagahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7479361
    Abstract: An objective of this invention is to prevent resist poisoning and sensitivity deterioration in a chemically amplified resist. The chemically amplified resist comprises a base resin, a photoacid generator and a salt exhibiting buffer effect in the base resin.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: January 20, 2009
    Assignee: Nec Electronics Corporation
    Inventors: Seiji Nagahara, Masayuki Hiroi
  • Patent number: 7440077
    Abstract: The exposure apparatus of the invention includes a chamber 1 housing an exposure apparatus body 6 provided with an illumination optical system 2, a reticle 3, a projection lens 4 and a stage 5, gas supply units 7, 13, 17 and 18 that are disposed in the chamber 1 and supply gas taken in from the outside of the chamber 1 to the vicinities of the reticle 3 and stage 5 and a wet filter 10 which is disposed in the vicinity of a gas intake 8 from which the gas is supplied to the gas supply units 7, 13, 17 and 18 and forms a water film through which the gas passes.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: October 21, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Nagahara
  • Publication number: 20080233518
    Abstract: With the damascene process in which an interconnection is formed using a conventional chemically amplified positive photoresist composition, there arises a problem that the photoresist within the via hole (as well as in its vicinity) may remain even after the exposure and the development are carried out. The present invention relates to a chemically amplified resist composition comprising, at least, a photo acid generator, a quencher and a salt having a buffering function for an acid which is generated from the acid generator by irradiation, wherein the salt having the buffering function for the acid generated from the acid generator is a salt derived from a long chain alkylbenzenesulfonic acid or a long chain alkoxybenzenesulfonic acid and an organic amine that is a basic compound.
    Type: Application
    Filed: May 28, 2008
    Publication date: September 25, 2008
    Applicants: NEC ELECTRONICS CORPORATION, SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Seiji Nagahara, Satoshi Watanabe, Kazunori Maeda
  • Patent number: 7396633
    Abstract: With the damascene process in which an interconnection is formed using a conventional chemically amplified positive photoresist composition, there arises a problem that the photoresist within the via hole (as well as in its vicinity) may remain even after the exposure and the development are carried out. The present invention relates to a chemically amplified resist composition comprising, at least, a photo acid generator, a quencher and a salt having a buffering function for an acid which is generated from the acid generator by irradiation, wherein the salt having the buffering function for the acid generated from the acid generator is a salt derived from a long chain alkylbenzenesulfonic acid or a long chain alkoxybenzenesulfonic acid and an organic amine that is a basic compound.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 8, 2008
    Assignees: NEC Electronics Corporation, Shin-Etsu Chemical Co., Ltd.
    Inventors: Seiji Nagahara, Satoshi Watanabe, Kazunori Maeda
  • Patent number: 7217654
    Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: May 15, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
  • Publication number: 20070096331
    Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.
    Type: Application
    Filed: December 18, 2006
    Publication date: May 3, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
  • Publication number: 20060152695
    Abstract: The exposure apparatus of the invention includes a chamber 1 housing an exposure apparatus body 6 provided with an illumination optical system 2, a reticle 3, a projection lens 4 and a stage 5, gas supply units 7, 13, 17 and 18 that are disposed in the chamber 1 and supply gas taken in from the outside of the chamber 1 to the vicinities of the reticle 3 and stage 5 and a wet filter 10 which is disposed in the vicinity of a gas intake 8 from which the gas is supplied to the gas supply units 7, 13, 17 and 18 and forms a water film through which the gas passes.
    Type: Application
    Filed: January 4, 2006
    Publication date: July 13, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Seiji Nagahara
  • Publication number: 20050124168
    Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
    Type: Application
    Filed: October 21, 2004
    Publication date: June 9, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
  • Publication number: 20040259373
    Abstract: An objective of this invention is to prevent resist poisoning and sensitivity deterioration in a chemically amplified resist. The chemically amplified resist comprises a base resin, a photoacid generator and a salt exhibiting buffer effect in the base resin.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 23, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Seiji Nagahara, Masayuki Hiroi
  • Publication number: 20040259029
    Abstract: With the damascene process in which an interconnection is formed using a conventional chemically amplified positive photoresist composition, there arises a problem that the photoresist within the via hole (as well as in its vicinity) may remain even after the exposure and the development are carried out. The present invention relates to a chemically amplified resist composition comprising, at least, a photo acid generator, a quencher and a salt having a buffering function for an acid which is generated from the acid generator by irradiation, wherein the salt having the buffering function for the acid generated from the acid generator is a salt derived from a long chain alkylbenzenesulfonic acid or a long chain alkoxybenzenesulfonic acid and an organic amine that is a basic compound.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 23, 2004
    Applicants: NEC ELECTRONICS CORPORATION, SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Seiji Nagahara, Satoshi Watanabe, Kazunori Maeda
  • Patent number: 6800551
    Abstract: To provide a chemical amplification type positive photoresist composition suited to resist patterning of a substrate presenting surface step differences, a method for manufacturing the semiconductor device employing this composition, and a semiconductor substrate. In a method for manufacturing a semiconductor device, a resist film is formed using a chemical amplification type positive photoresist composition, comprised of a base resin and a basic compound added to the base resin at a rate of 1 to 100 mmol to 100 g of the base resin, on a substrate halving surface step differences and into which the organic removing solution is deposited or oozed, and a predetermined area of the resist film is exposed to light to form a resist pattern.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: October 5, 2004
    Assignees: NEC Electronics Corporation, Shin-Etsu Chemical Co., Ltd.
    Inventors: Seiji Nagahara, Toyohisa Sakurada, Takao Yoshihara
  • Patent number: 6774028
    Abstract: A multi-layer wiring structure is formed by using a dual damascene method. First and second interlayer insulating films formed on a lower conductor layer are etched by using a first photo resist film as a mask to form a via hole. An anti-reflective coating is formed on the second interlayer insulating film such that a portion of the via hole is also filled therewith. A second photo resist film is formed on the anti-reflective coating such that a remaining portion of the via hole is also filled therewith. A development rate of an exposed portion of the second photo resist film is selected to be 250-700 nm/second. A wiring trench pattern is formed in the second photo resist film, and the anti-reflective coating and the second interlayer insulating film is etched by using the second photo resist film as a mask to form a wiring trench. The via hole and the wiring trench are filled with a conductive material to form a via and a wiring conductor.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: August 10, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Seiji Nagahara
  • Publication number: 20030170993
    Abstract: A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
    Type: Application
    Filed: November 26, 2002
    Publication date: September 11, 2003
    Inventors: Seiji Nagahara, Kazutoshi Shiba, Nobuaki Hamanaka, Tatsuya Usami, Takashi Yokoyama
  • Publication number: 20030157806
    Abstract: To provide a chemical amplification type positive photoresist composition suited to resist patterning of a substrate presenting surface step differences, a method for manufacturing the semiconductor device employing this composition, and a semiconductor substrate. In a method for manufacturing a semiconductor device, a resist film is formed using a chemical amplification type positive photoresist composition, comprised of a base resin and a basic compound added to the base resin at a rate of 1 to 100 mmol to 100 g of the base resin, on a substrate halving surface step differences and into which the organic removing solution is deposited or oozed, and a predetermined area of the resist film is exposed to light to form a resist pattern.
    Type: Application
    Filed: December 3, 2002
    Publication date: August 21, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Seiji Nagahara, Toyohisa Sakurada, Takao Yoshihara
  • Publication number: 20020192945
    Abstract: A multi-layer wiring structure is formed by using a dual damascene method. First and second interlayer insulating films formed on a lower conductor layer are etched by using a first photo resist film as a mask to form a via hole. An anti-reflective coating is formed on the second interlayer insulating film such that a portion of the via hole is also filled therewith. A second photo resist film is formed on the anti-reflective coating such that a remaining portion of the via hole is also filled therewith. A development rate of an exposed portion of the second photo resist film is selected to be 250-700 nm/second. A wiring trench pattern is formed in the second photo resist film, and the anti-reflective coating and the second interlayer insulating film is etched by using the second photo resist film as a mask to form a wiring trench. The via hole and the wiring trench are filled with a conductive material to form a via and a wiring conductor.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 19, 2002
    Applicant: NEC Corporation
    Inventor: Seiji Nagahara