Patents by Inventor Seiji Nagai
Seiji Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090310328Abstract: A folding electronic device includes a fixed casing, a movable casing, and a hinge device connecting the fixed casing and the movable casing to allow rotational movement of the movable casing. The movable casing is openable with respect to the fixed casing. The hinge device has an axis extending over a land portion of the fixed casing and a land portion of the movable casing. A projection is provided in any of the following: at least one of end faces of the land portion of the fixed casing and an end face, opposed to one of the end faces, of the land portion of the movable casing. As the movable casing changes from a closed state to an open state, a gap between the projection and an end face opposed to the projection is increased.Type: ApplicationFiled: February 27, 2009Publication date: December 17, 2009Applicant: FUJITSU LIMITEDInventors: Chikara KOBAYASHI, Seiji Nagai, Yutaka Kawahigashi
-
Publication number: 20090294909Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.Type: ApplicationFiled: May 20, 2009Publication date: December 3, 2009Applicant: OSAKA UNIVERSITYInventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
-
Publication number: 20090197118Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Applicant: TOYODA GOSEI CO.,LTD.Inventors: Seiji NAGAI, Shiro YAMAZAKI, Takayuki SATO, Yasuhide YAKUSHI, Koji OKUNO, Koichi GOSHONOO
-
Patent number: 7491984Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.Type: GrantFiled: November 2, 2004Date of Patent: February 17, 2009Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
-
Publication number: 20080271665Abstract: In the production of GaN through the flux method, deposition of miscellaneous crystals on the nitrogen-face of a GaN self-standing substrate and waste of raw materials are prevented. Four arrangements of crucibles and a GaN self-standing substrate are exemplified. In FIG. 1A, a nitrogen-face of a self-standing substrate comes into close contact with a sloped flat inner wall of a crucible. In FIG. 1B, a nitrogen-face of a self-standing substrate comes into close contact with a horizontally facing flat inner wall of a crucible, and the substrate is fixed by means of a jig. In FIG. 1C, a jig is provided on a flat bottom of a crucible, and two GaN self-standing substrates are fixed by means of the jig so that the nitrogen-faces of the substrates come into close contact with each other. In FIG. 1D, a jig is provided on a flat bottom of a crucible, and a GaN self-standing substrate is fixed on the jig so that the nitrogen-face of the substrate is covered with the jig.Type: ApplicationFiled: April 23, 2008Publication date: November 6, 2008Applicants: TOYODA GOSEI CO., LTD., NGK INSULATORS, LTD.Inventors: Shiro YAMAZAKI, Seiji NAGAI, Takayuki SATO, Katsuhiro IMAI, Makoto IWAI, Takatomo SASAKI, Yusuke MORI, Fumio KAWAMURA
-
Publication number: 20080223286Abstract: Objects of the invention are to further enhance crystallinity and crystallinity uniformity of a semiconductor crystal produced through the flux method, and to effectively enhance the production yield of the semiconductor crystal. The c-axis of a seed crystal including a GaN single-crystal layer is aligned in a horizontal direction (y-axis direction), one a-axis of the seed crystal is aligned in the vertical direction, and one m-axis is aligned in the x-axis direction. Thus, three contact points at which a supporting tool contacts the seed crystal are present on m-plane. The supporting tool has two supporting members, which extend in the vertical direction. One supporting member has an end part, which is inclined at 30° with respect to the horizontal plane ?. The reasons for supporting a seed crystal at m-plane thereof are that m-plane exhibits a crystal growth rate, which is lower than that of a-plane, and that desired crystal growth on c-plane is not inhibited.Type: ApplicationFiled: February 29, 2008Publication date: September 18, 2008Applicants: TOYODA GOSEI CO., LTD., NGK INSULATORS, LTD.,, OSAKA UNIVERSIITYInventors: Seiji Nagai, Shiro Yamazaki, Takayuki Sato, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
-
Publication number: 20080223288Abstract: An object of the invention is to carry out the flux method with improved work efficiency while maintaining the purity of flux at high level and saving flux material cost. The sodium-purifying apparatus includes a sodium-holding-and-management apparatus for maintaining purified sodium (Na) in a liquid state. Liquid sodium is supplied into a sodium-holding-and-management apparatus through a liquid-sodium supply piping maintained at 100° C. to 200° C. The sodium-holding-and-management apparatus further has an argon-gas-purifying apparatus for controlling the condition of argon (Ar) gas that fills the internal space thereof. Thus, by opening and closing a faucet at desired timing, purified liquid sodium (Na) supplied from the sodium-purifying apparatus can be introduced into a crucible as appropriate via the liquid-sodium supply piping, the sodium-holding-and-management apparatus, and the piping.Type: ApplicationFiled: March 11, 2008Publication date: September 18, 2008Applicants: TOYODA GOSEI CO., LTD., NGK INSULATORS, LTD., Yusuke MORIInventors: Shiro Yamazaki, Koji Hirata, Takayuki Sato, Seiji Nagai, Katsuhiro Imai, Makoto Iwai, Shuhei Higashihara, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
-
Patent number: 7163876Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.Type: GrantFiled: March 12, 2002Date of Patent: January 16, 2007Assignees: Toyoda Gosei Co., Ltd, Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
-
Patent number: 7141444Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate.Type: GrantFiled: March 12, 2001Date of Patent: November 28, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Yuta Tezen, Hiroshi Yamashita, Seiji Nagai, Toshio Hiramatsu
-
Patent number: 7052979Abstract: When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily.Type: GrantFiled: February 12, 2002Date of Patent: May 30, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Kazuyoshi Tomita, Shiro Yamazaki, Yuta Tezen, Toshio Hiramatsu
-
Patent number: 7011707Abstract: A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.Type: GrantFiled: March 27, 2002Date of Patent: March 14, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Kazuyoshi Tomita, Yoshihiro Irokawa, Kenji Ito
-
Patent number: 6964705Abstract: A seed layer as a laminate of a GaN layer (second seed layer) and an AlN buffer layer (first seed layer) is formed on a sapphire substrate. A front surface thereof is etched in the form of stripes with a stripe width (seed width) of about 5 ?m, a wing width of about 15 ?m and a depth of about 0.5 ?m. As a result, mesa portions each shaped like nearly a rectangle in sectional view are formed. Non-etched portions each having the seed multilayer as its flat top portion are arranged at arrangement intervals of L?20 ?m. Part of the sapphire substrate is exposed in trough portions of wings. The ratio S/W of the seed width to the wing width is preferably selected to be in a range of from about ? to about ?. Then, a semiconductor crystal A is grown to obtain a thickness of not smaller than 50 ?m. The semiconductor crystal is separated from the starting substrate to thereby obtain a high-quality single crystal independent of the starting substrate.Type: GrantFiled: July 17, 2003Date of Patent: November 15, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Akira Kojima, Kazuyoshi Tomita
-
Publication number: 20050093099Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.Type: ApplicationFiled: November 2, 2004Publication date: May 5, 2005Applicant: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
-
Patent number: 6861305Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, strip, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer is 31 can be prevented.Type: GrantFiled: March 29, 2001Date of Patent: March 1, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
-
Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices
Patent number: 6855620Abstract: A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth.Type: GrantFiled: March 2, 2001Date of Patent: February 15, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Seiji Nagai, Yuta Tezen -
Patent number: 6844246Abstract: A GaN layer 32 grows in vertical direction on a GaN layer 31 where neither a first mask 41m nor a second mask 42m is formed. When thickness of the GaN layer 32 becomes larger than that of the first mask 41m, it began to grown in lateral direction so as to cover the first mask 41m. Because the second mask 42m is not formed on the upper portion of the first mask 41m, the GaN layer 32 grows in vertical direction. On the contrary, at the upper region of the GaN layer 31 where the mask 41m is not formed, the second mask 42m is formed like eaves, the growth of the GaN layer 32 stops and threading dislocations propagated with vertical growth also stops there. The GaN layer 32 grows in vertical direction so as to penetrate the region where neither the first mask 41m nor the second mask 42m is formed. When the height of the GaN layer 32 becomes larger than that of the second mask 42m, the GaN layer 32 begins to grow in lateral direction again and covers the second mask 42m.Type: GrantFiled: March 19, 2002Date of Patent: January 18, 2005Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Kazuyoshi Tomita, Masahito Kodama
-
Patent number: 6821800Abstract: In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1-Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1-Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.Type: GrantFiled: December 23, 2002Date of Patent: November 23, 2004Assignee: Toyoda Gosei Co., Ltd.Inventors: Norikatsu Koide, Shinya Asami, Junichi Umezaki, Masayoshi Koike, Shiro Yamasaki, Seiji Nagai
-
Publication number: 20040219702Abstract: In the epitaxial growth process in which each growth region D is zoned by a mask 2 formed in grid pattern, because a consumption region C of the Group III nitride compound semiconductor is formed in the central portion of each band of the mask 2 between each adjacent edge portion of the growth region D, Group III or Group V raw material is never unnecessarily supplied to the edge portion of the growth region D. As a result, difference of Group III or Group V rare material supply amount to the edge portion and central portion of the device formation region D is suppressed and the edge portion of the device region may not be convexity.Type: ApplicationFiled: January 8, 2004Publication date: November 4, 2004Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
-
Patent number: 6790279Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.Type: GrantFiled: July 2, 2002Date of Patent: September 14, 2004Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Seiji Nagai
-
Publication number: 20040123796Abstract: When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily.Type: ApplicationFiled: October 9, 2003Publication date: July 1, 2004Inventors: Seiji Nagai, Kazuyoshi Tomita, Shiro Yamazaki, Yuta Tezen, Toshio Hiramatsu