Patents by Inventor Seiji Nakahata

Seiji Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090209091
    Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 20, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Publication number: 20090197398
    Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.
    Type: Application
    Filed: April 7, 2009
    Publication date: August 6, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Seiji Nakahata
  • Publication number: 20090189253
    Abstract: AlxInyGa1-x-yN(0?x?1; 0?x?1; 0?x+y?1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN(0?x?1; 0?y?1; 0?x+y?1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S. Chip-separation is done instantly by the high power laser irradiation or mechanical shock without cutting the substrate S.
    Type: Application
    Filed: March 24, 2009
    Publication date: July 30, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji NAKAHATA, Koji Uematsu, Hideaki Nakahata
  • Patent number: 7556687
    Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: July 7, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Publication number: 20090155989
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts not burying the facets, maintaining the convex facet hills on ? and the network concavities on excluding dislocations in the facet hills down to the outlining concavities on forming a defect accumulating region H on decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Application
    Filed: February 19, 2009
    Publication date: June 18, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji UEMATSU, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Publication number: 20090127564
    Abstract: A GaN substrate manufacturing method characterized in including a step of processing the surface of a substrate composed of a GaN single crystal into a concavely spherical form, based on differences in orientation of the crystallographic axis across the substrate surface. Processing the GaN substrate surface into a concavely spherical form reduces, in the post-process GaN substrate surface, differences in orientation of the crystallographic axis with respect to a normal. Furthermore, employing to manufacture semiconductor devices a GaN substrate in which differences in orientation of the crystallographic axis have been reduced makes it possible to uniformize in device characteristics a plurality of semiconductor devices fabricated from a single GaN substrate, which contributes to improving yields in manufacturing the semiconductor devices.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 21, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masato Irikura, Seiji Nakahata
  • Patent number: 7534295
    Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: May 19, 2009
    Assignee: Sumitomo Electric Industries, Ltd
    Inventor: Seiji Nakahata
  • Patent number: 7534310
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: May 19, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
  • Patent number: 7528055
    Abstract: AlxInyGa1-x-yN (0?x?1; 0?x?1; 0?x+y?1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN (0?x?1; 0?y?1; 0?x+y?1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: May 5, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Hideaki Nakahata
  • Publication number: 20090108297
    Abstract: A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 ?m to 100 ?m are arranged at an interval Dw from 250 ?m to 2000 ?m, growing a nitride semiconductor crystal on the underlying substrate with an HVPE method at a growth temperature from 1040° C. to 1150° C. by supplying a group III raw material gas and a group V raw material gas of which group V/group III ratio R5/3 is set to 1 to 10 and a gas containing iron, and removing the underlying substrate, to thereby obtain a free-standing semi-insulating nitride semiconductor substrate having a specific resistance not smaller than 1×105 ?cm and a thickness not smaller than 100 ?m. Thus, the semi-insulating nitride semiconductor crystal substrate in which warpage is less and cracking is less likely can be obtained.
    Type: Application
    Filed: October 23, 2008
    Publication date: April 30, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Fumitaka SATO, Seiji NAKAHATA, Makoto KIYAMA
  • Publication number: 20090071394
    Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Applicant: SUMITOMO ELECTRONIC INDUSTRIES, LTD.
    Inventors: Seiji NAKAHATA, Ryu HIROTA, Kensaku MOTOKI, Takuji OKAHISA, Koji UEMATSU
  • Patent number: 7485484
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Alternatively, the III-V crystal manufacturing method is characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 3, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Patent number: 7473315
    Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: January 6, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
  • Publication number: 20080308906
    Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 18, 2008
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki OSADA, Hitoshi Kasai, Keiji Ishibashi, Seiji Nakahata, Takashi Kyono, Katsushi Akita, Yoshiki Miura
  • Publication number: 20080308815
    Abstract: Affords a GaN substrate from which enhanced-emission-efficiency light-emitting and like semiconductor devices can be produced, an epi-substrate in which an epitaxial layer has been formed on the GaN substrate principal surface, a semiconductor device, and a method of manufacturing the GaN substrate. The GaN substrate is a substrate having a principal surface with respect to whose normal vector the [0001] plane orientation is inclined in two different off-axis directions.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 18, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hitoshi Kasai, Keiji Ishibashi, Seiji Nakahata, Katsushi Akita, Takashi Kyono, Yoshiki Miura
  • Publication number: 20080308814
    Abstract: There is disclosed a method for forming a gallium nitride layer of which resistivity is 1×106?·cm or more, including steps of: forming a gallium nitride layer containing iron on a substrate; and heating said gallium nitride layer formed on said substrate.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 18, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji NAKAHATA, Fumitaka Sato, Yoshiki Miura, Akinori Koukitu, Yoshinao Kumagai
  • Publication number: 20080296585
    Abstract: A method of producing a GaN crystal is directed to growing a GaN crystal on a GaN seed crystal substrate. The method includes the steps of preparing a GaN seed crystal substrate including a first dopant such that the thermal expansion coefficient of the GaN seed crystal substrate becomes greater than that of the GaN crystal, and growing the GaN crystal to a thickness of at least 1 mm on the GaN seed crystal substrate. Accordingly, there can be provided a method of producing a GaN crystal that can suppress generation of a crack and grow a thick GaN crystal, and a GaN crystal substrate.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Naoki MATSUMOTO, Fumitaka Sato, Seiji Nakahata, Takuji Okahisa, Koji Uematsu
  • Publication number: 20080299748
    Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Alternatively, the III-V crystal manufacturing method is characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.
    Type: Application
    Filed: August 8, 2008
    Publication date: December 4, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Publication number: 20080283968
    Abstract: A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has been melted, and growing group III-nitride semiconductor crystal is provided. The group III-nitride semiconductor crystal attaining a small absorption coefficient and an efficient method of manufacturing the same, as well as a group III-nitride semiconductor device attaining high light emission intensity can thus be provided.
    Type: Application
    Filed: March 30, 2005
    Publication date: November 20, 2008
    Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
  • Publication number: 20080271667
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura