Patents by Inventor Seiji Nakahata

Seiji Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070148920
    Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 28, 2007
    Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Publication number: 20070062440
    Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).
    Type: Application
    Filed: November 22, 2006
    Publication date: March 22, 2007
    Inventors: Fumitaka Sato, Seiji Nakahata
  • Publication number: 20070054476
    Abstract: AlxInyGa1-x-yN (0?x?1; 0?x?1; 0?x+y?1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN (0?x?1; 0?y?1; 0?x+y?1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Inventors: Seiji Nakahata, Koji Uematsu, Hideaki Nakahata
  • Publication number: 20070012943
    Abstract: A method of manufacturing a group III nitride semiconductor substrate includes the growth step of epitaxially growing a first group III nitride semiconductor layer on an underlying substrate, and the process step of forming a first group III nitride semiconductor substrate by cutting and/or surface-polishing the first group III nitride semiconductor layer. In the growth step, at least one element selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is added as an impurity element by at least 1×1017 cm?3 to the first group III nitride semiconductor layer. A group III nitride semiconductor substrate having controlled resistivity and low dislocation density and a manufacturing method thereof can thus be provided.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 18, 2007
    Inventors: Takuji Okahisa, Hideaki Nakahata, Seiji Nakahata
  • Publication number: 20060292728
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Application
    Filed: June 23, 2006
    Publication date: December 28, 2006
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20060272572
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts ?, not burying the facets, maintaining the convex facet hills on ? and the network concavities on ?, excluding dislocations in the facet hills down to the outlining concavities on ?, forming a defect accumulating region H on ?, decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 7, 2006
    Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Publication number: 20060273343
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1?x?yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Application
    Filed: August 10, 2006
    Publication date: December 7, 2006
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
  • Publication number: 20060213429
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Application
    Filed: May 17, 2006
    Publication date: September 28, 2006
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
  • Patent number: 7112826
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: September 26, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu
  • Patent number: 7105865
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 12, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
  • Patent number: 7087114
    Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: August 8, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
  • Publication number: 20060054942
    Abstract: A light emitting device which has increased light emitting amount without changing its size is provided. The light emitting device is characterized in that a semiconductor layer 30 is formed on an uneven surface 1a of an uneven substrate 1. The light emitting device of the invention can be configured such that the uneven substrate and the semiconductor layer are both made of AlxGayIn1-x-yN (0?x, 0?y, x+y?1); each of the planes forming the uneven surface of the uneven substrate has at least one plane index selected from among (11-2L) and (1-10L) in which L represents an integer from 1 to 4; and the angle formed between each of the planes forming the uneven surface of the uneven substrate and the base plane is from 35° to 80°.
    Type: Application
    Filed: May 31, 2004
    Publication date: March 16, 2006
    Inventor: Seiji Nakahata
  • Publication number: 20060027896
    Abstract: Fracture toughness of AlGaN single-crystal substrate is improved and its absorption coefficient reduced. A nitride semiconductor single-crystal substrate has a composition represented by the formula AlxGa1-xN (0?x?1), and is characterized by having a fracture toughness of (1.2?0.7x) MPa·m1/2 or greater and a surface area of 20 cm2, or, if the substrate has a composition represented by the formula AlxGa1-xN (0.5?x?1), by having an absorption coefficient of 50 cm?1 or less in a 350 to 780 nm total wavelength range.
    Type: Application
    Filed: August 3, 2005
    Publication date: February 9, 2006
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke Fujiwara, Seiji Nakahata
  • Publication number: 20060012011
    Abstract: A method of processing a surface of a nitride semiconductor crystal, wherein a surface of a nitride semiconductor crystal is brought into contact with a liquid containing at least Na, Li or Ca as a processing solution. In the method, the processing solution can be a liquid containing at least Na, having an Na content of 5-95 mol %. The processing solution can be a liquid containing at least Li, having an Li content of 5-100 mol %. A nitride semiconductor crystal having a maximum depth of a surface scratch of at most 0.01 ?m or an average thickness of a damaged layer of at most 2 ?m. Consequently, a method of processing a surface of a nitride semiconductor crystal with a decreased depth of a surface scratch or a decreased thickness of a damaged layer, and a nitride semiconductor crystal obtained with the method can be provided.
    Type: Application
    Filed: June 3, 2004
    Publication date: January 19, 2006
    Inventors: Seiji Nakahata, Ryu Hirota, Keiji Ishibashi, Takatomo Sasaki, Yusuke Mori
  • Publication number: 20050277214
    Abstract: A method of producing a nitride single crystal includes the step of forming a material transport medium layer containing a compound of rare earth element on a surface of a nitride crystal, and the step of making a seed crystal in contact with the material transport medium layer to grow a nitride single crystal on the seed crystal. The material transport medium layer contains the compound of rare earth element and at least one compound selected from a group of aluminum compound, alkaline earth compound and transition metal compound. With this producing method, a large nitride single crystal having a crystal size of at least 10 mm is obtained.
    Type: Application
    Filed: June 10, 2004
    Publication date: December 15, 2005
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Seiji Nakahata
  • Publication number: 20050257733
    Abstract: A group III nitride crystal having a small dislocation density and good quality and a production method for the group III nitride crystal are provided. The production method for the group III nitride crystal is characterized by growing a group III nitride crystal film 2 on a substrate 1, depositing a metallic film 3 thereon and, then, not only changing the metallic film 3 into a metallic nitride film 4 and, further, generating a pore 4h, but also forming a void portion 2b in the group III nitride crystal film 2 by performing a thermal treatment and, thereafter, filling the void portion 2b by a group III nitride crystal 5 for filling by further growing a group III nitride crystal and, subsequently, growing a group III nitride crystal 6 on the metallic nitride film 4.
    Type: Application
    Filed: May 24, 2004
    Publication date: November 24, 2005
    Inventor: Seiji Nakahata
  • Publication number: 20050227472
    Abstract: A method of manufacturing a group III-V crystal is made available by which good-quality group III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. A method of manufacturing a group III-V crystal, characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Additionally, a method of manufacturing a group III-V crystal, characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.
    Type: Application
    Filed: April 1, 2004
    Publication date: October 13, 2005
    Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
  • Publication number: 20050183658
    Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).
    Type: Application
    Filed: March 1, 2005
    Publication date: August 25, 2005
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
  • Publication number: 20050164419
    Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.
    Type: Application
    Filed: January 24, 2005
    Publication date: July 28, 2005
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno
  • Publication number: 20050161697
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?×?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Application
    Filed: January 25, 2005
    Publication date: July 28, 2005
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu