Patents by Inventor Seiji Narui

Seiji Narui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190122708
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Patent number: 10185652
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Patent number: 10163469
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20180357156
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Publication number: 20180341575
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Publication number: 20180151207
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Patent number: 9472253
    Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Chikara Kondo
  • Patent number: 9412432
    Abstract: A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 9, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Patent number: 9355705
    Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: May 31, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Kiyohiro Furutani, Seiji Narui
  • Publication number: 20160042782
    Abstract: [Problem] To regenerate the charge of a memory cell having reduced information retention characteristics using a target row refresh operation. [Solution] A semiconductor storage device is provided with a memory cell array (11) comprising a plurality of word lines including word lines (WLI, WL2) that are adjacent to one another; and a TRR address conversion unit (53) that selects the word line (WL1) in response to the input of an address signal (IADD) indicating a first value while in a first operation mode and selects the word line (WL2) in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation.
    Type: Application
    Filed: March 13, 2014
    Publication date: February 11, 2016
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Publication number: 20150213860
    Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.
    Type: Application
    Filed: January 28, 2015
    Publication date: July 30, 2015
    Inventors: Seiji Narui, Chikara Kondo
  • Patent number: 9081402
    Abstract: A method for controlling power supply current in a CMOS circuit, the method including applying a first predetermined voltage to a diode connected n-channel replica transistor, the n-channel replica transistor operating in weak inversion, applying a first substrate voltage to the substrate of the n-channel replica transistor so that the current flowing in the n-channel replica transistor equals a first predetermined target current, and applying the first substrate voltage to substrates of n-channel transistors in the CMOS circuit.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: July 14, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
  • Publication number: 20150131389
    Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).
    Type: Application
    Filed: January 12, 2015
    Publication date: May 14, 2015
    Applicant: PS4 LUXCO S.A.R.L.
    Inventors: Kiyohiro FURUTANI, Seiji NARUI
  • Patent number: 8988952
    Abstract: Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: March 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Atsushi Hiraishi, Toshio Sugano, Seiji Narui, Yasuhiro Takai
  • Patent number: 8971132
    Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Kiyohiro Furutani, Seiji Narui
  • Patent number: 8947128
    Abstract: Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Chiaki Dono, Seiji Narui, Seiichi Maruno
  • Patent number: 8902691
    Abstract: Disclosed herein is a device that includes a capacitor, a pumping circuit supplying a pumping signal changed between first and second potential to a first electrode of the capacitor, and an output circuit precharging a second electrode of the capacitor to a third potential different from the first and second potentials. The second electrode of the capacitor is thereby changed from the third potential to a fourth potential higher than the third potential when the pumping signal is changed from the first potential to the second potential.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 2, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Seiji Narui, Hitoshi Tanaka
  • Patent number: 8885432
    Abstract: A method for refreshing memory cells in a DRAM includes receiving a refresh command, receiving a refresh mode specifying signal in synchronization with the refresh command, refreshing a first quantity of memory cells when the refresh mode specifying signal has a first value, and refreshing a second quantity of memory cells, at least double the first quantity, when the refresh mode specifying signal has a second value.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Seiji Narui
  • Publication number: 20140300408
    Abstract: A method for controlling power supply current in a CMOS circuit, the method including applying a first predetermined voltage to a diode connected n-channel replica transistor, the n-channel replica transistor operating in weak inversion, applying a first substrate voltage to the substrate of the n-channel replica transistor so that the current flowing in the n-channel replica transistor equals a first predetermined target current, and applying the first substrate voltage to substrates of n-channel transistors in the CMOS circuit
    Type: Application
    Filed: June 20, 2014
    Publication date: October 9, 2014
    Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
  • Patent number: 8773884
    Abstract: A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: July 8, 2014
    Inventor: Seiji Narui