Patents by Inventor Seiji Narui

Seiji Narui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10777232
    Abstract: An apparatus that includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Seiji Narui
  • Publication number: 20200251148
    Abstract: An apparatus that includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 6, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Seiji NARUI
  • Publication number: 20200233828
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10664432
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Publication number: 20200126603
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20200126993
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Yuki Ebihara
  • Patent number: 10614024
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10553263
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20190361835
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10489312
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Publication number: 20190304512
    Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Seiji Narui
  • Publication number: 20190122708
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Patent number: 10185652
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Patent number: 10163469
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20180357156
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Publication number: 20180341575
    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Homare Sato, Chikara Kondo
  • Publication number: 20180151207
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Patent number: 9472253
    Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: October 18, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Chikara Kondo
  • Patent number: 9412432
    Abstract: A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 9, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Patent number: 9355705
    Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: May 31, 2016
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Kiyohiro Furutani, Seiji Narui