Abstract: A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.

Abstract: A system includes a first circuit and a second circuit that are constituted by a semiconductor device, the second circuit controlling the first circuit. The first circuit includes an interface unit that performs communication with the second circuit, a plurality of sense amplifiers including a first sense amplifier, each of the plurality of sense amplifiers performing communication with the interface unit, a first global bit line, a dummy global bit line, a plurality of first memory blocks, each of the first memory blocks including a first hierarchy switch that is connected to the first global bit line, a dummy memory block including a dummy hierarchy switch that is connected to the dummy global bit line, and a first dummy local bit line connected to the dummy global bit line, and a control circuit that controls the first hierarchy switches and the dummy hierarchy switch.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).

Abstract: Disclosed herein is a device that includes a capacitor, a pumping circuit supplying a pumping signal changed between first and second potential to a first electrode of the capacitor, and an output circuit precharging a second electrode of the capacitor to a third potential different from the first and second potentials. The second electrode of the capacitor is thereby changed from the third potential to a fourth potential higher than the third potential when the pumping signal is changed from the first potential to the second potential.

Abstract: A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch and a local bit line that is connected to the global bit line via the hierarchy switch, a dummy memory block that includes a dummy hierarchy switch and a dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch, and a control circuit that activates any one of hierarchy switches and the dummy hierarchy switch. With this configuration, it is possible to obtain the same memory capacity between a memory mat located at an edge and the other memory mat.

Abstract: A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

Abstract: A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.

Abstract: To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.

Abstract: A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.

Abstract: To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.

Abstract: To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2n times in response to one supply of the refresh command, where n is an integer equal to or larger than 0 and equal to or less than k. The value of n is variable based on a refresh-mode specifying signal supplied from outside in synchronization with the refresh command. With this configuration, for example, a frequency of generation of the refresh execution signal in response to one supply of the refresh command can be changed dynamically, flexible control can be performed by a controller.

Abstract: A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.

Abstract: To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.

Abstract: A semiconductor device includes a global bit line, a dummy global bit line that is shorter than the global bit line, a sense amplifier that amplifies a potential difference between the global bit line and the dummy global bit line, a plurality of memory blocks each including a hierarchy switch and a local bit line that is connected to the global bit line via the hierarchy switch, a dummy memory block that includes a dummy hierarchy switch and a dummy local bit line that is connected to the dummy global bit line via the dummy hierarchy switch, and a control circuit that activates any one of hierarchy switches and the dummy hierarchy switch. With this configuration, it is possible to obtain the same memory capacity between a memory mat located at an edge and the other memory mat.

Abstract: Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.

Abstract: A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.

Abstract: A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.

Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized(FIG. 2).

Abstract: To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.

Abstract: A semiconductor memory device includes multiple mats arranged in an array, each including multiple memory cells storing a charge as information, and multiple power-supply lines, one end of each line of the lines being connected in common to an internal power supply which decreases or increases a voltage which is supplied from an external power source. The power-supply lines extend in a given direction in an area in which the multiple mats are formed and the other end of each line of the multiple power-supply lines is connected in common on the edge mat.