Patents by Inventor Seiji Noguchi
Seiji Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190097030Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.Type: ApplicationFiled: November 29, 2018Publication date: March 28, 2019Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
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Publication number: 20190067530Abstract: A blue light-emitting Eu-activated silicate phosphor having a constitutional formula of Sr3MgSi2O3 which contains Eu in an amount of 0.001 to 0.2 mol per one mole of Mg and further a rare earth metal element selected from the group consisting of Sc, Y, Gd, Tb and La in an amount of 0.0001 to 0.03 mol, per one mole of Mg, gives an emission with enhanced emission strength when it is excited with a light having a wavelength in the region of 350 to 430 nm.Type: ApplicationFiled: October 29, 2018Publication date: February 28, 2019Inventors: Kouichi FUKUDA, Jin AMAGAI, Seiji NOGUCHI, Toru INAGAKI, Masaki TANAKA
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Patent number: 10030150Abstract: A fine magnesium oxide particle dispersion liquid containing an aprotic solvent, and fine magnesium oxide particles that are dispersed in the aprotic solvent, wherein the dispersion liquid has D50 of 200 nm or less in a particle size distribution as measured by a dynamic light scattering method, and has a content rate of coarse particles having an average particle diameter of 500 nm or more of less than 1%, and a method for producing the fine magnesium oxide particle dispersion liquid.Type: GrantFiled: March 23, 2015Date of Patent: July 24, 2018Assignee: UBE MATERIAL INDUSTRIES, LTD.Inventors: Seiji Noguchi, Yuzo Kato, Masayuki Fujimoto
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Patent number: 9938443Abstract: A magnesium oxide material includes a magnesium oxide powder treated with a halogen compound and a silane coupling agent. A method of producing a magnesium oxide material includes a step including preparing a magnesium oxide powder, a halogen compound treatment step including subjecting the magnesium oxide powder to a surface treatment with a halogen compound, and a silane coupling agent treatment step including subjecting the magnesium oxide powder to a surface treatment with a silane coupling agent.Type: GrantFiled: February 12, 2015Date of Patent: April 10, 2018Assignee: UBE MATERIAL INDUSTRIES, LTD.Inventors: Masayuki Fujimoto, Yuzo Kato, Seiji Noguchi
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Publication number: 20170373141Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.Type: ApplicationFiled: August 25, 2017Publication date: December 28, 2017Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATIONInventors: Souichi YOSHIDA, Seiji NOGUCHI, Kenji KOUNO, Hiromitsu TANABE
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Publication number: 20170141216Abstract: A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.Type: ApplicationFiled: January 26, 2017Publication date: May 18, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hitoshi ABE, Hiroshi MIYATA, Hidenori TAKAHASHI, Seiji NOGUCHI, Naoya SHIMADA
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Publication number: 20170096562Abstract: A fine magnesium oxide particle dispersion liquid containing an aprotic solvent, and fine magnesium oxide particles that are dispersed in the aprotic solvent, wherein the dispersion liquid has D50 of 200 nm or less in a particle size distribution as measured by a dynamic light scattering method, and has a content rate of coarse particles having an average particle diameter of 500 nm or more of less than 1%, and a method for producing the fine magnesium oxide particle dispersion liquid.Type: ApplicationFiled: March 23, 2015Publication date: April 6, 2017Applicant: Ube Materials Industries, Ltd.Inventors: Seiji Noguchi, Yuzo Kato, Masayuki Fujimoto
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Publication number: 20170044417Abstract: A magnesium oxide material includes a magnesium oxide powder treated with a halogen compound and a silane coupling agent. A method of producing a magnesium oxide material includes a step including preparing a magnesium oxide powder, a halogen compound treatment step including subjecting the magnesium oxide powder to a surface treatment with a halogen compound, and a silane coupling agent treatment step including subjecting the magnesium oxide powder to a surface treatment with a silane coupling agent.Type: ApplicationFiled: February 12, 2015Publication date: February 16, 2017Applicant: UBE MATERIAL INDUSTRIES, LTD.Inventors: Masayuki Fujimoto, Yuzo Kato, Seiji Noguchi
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Patent number: 9484343Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.Type: GrantFiled: March 9, 2015Date of Patent: November 1, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Seiji Noguchi, Hidenao Kuribayashi
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Publication number: 20160211424Abstract: A blue light-emitting Eu-activated silicate phosphor having a constitutional formula of Sr3MgSi2O8 which contains Eu in an amount of 0.001 to 0.2 mol per one mole of Mg and further a rare earth metal element selected from the group consisting of Sc, Y, Gd, Tb and La in an amount of 0.0001 to 0.03 mol, per one mole of Mg, gives an emission with enhanced emission strength when it is excited with a light having a wavelength in the region of 350 to 430 nm.Type: ApplicationFiled: March 29, 2016Publication date: July 21, 2016Inventors: Kouichi FUKUDA, Jin AMAGAI, Seiji NOGUCHI, Toru INAGAKI, Masaki TANAKA
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Patent number: 9378959Abstract: First, a first resist mask for forming an n+ emitter region is formed on the front surface of an n? semiconductor substrate. The first resist mask is left on the surface of the gate electrode. Next, a first ion implantation is performed with the first resist mask to form the n+ emitter region. At this time, as the first ion implantation, both a perpendicular ion implantation is performed at an implantation angle that is perpendicular to the substrate front surface, and an oblique ion implantation at an implantation angle that is tilted relative to the direction perpendicular to the substrate front surface. The oblique ion implantation widens a width of the n+ emitter region in the trench widthwise direction. Next, a second ion implantation is performed with a second resist mask to form a p+ contact region. Thereafter, a heat treatment is used to diffuse and activate the n+ emitter region and the p+ contact region.Type: GrantFiled: September 3, 2015Date of Patent: June 28, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventor: Seiji Noguchi
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Publication number: 20160086804Abstract: First, a first resist mask for forming an n+ emitter region is formed on the front surface of an n? semiconductor substrate. The first resist mask is left on the surface of the gate electrode. Next, a first ion implantation is performed with the first resist mask to form the n+ emitter region. At this time, as the first ion implantation, both a perpendicular ion implantation is performed at an implantation angle that is perpendicular to the substrate front surface, and an oblique ion implantation at an implantation angle that is tilted relative to the direction perpendicular to the substrate front surface. The oblique ion implantation widens a width of the n+ emitter region in the trench widthwise direction. Next, a second ion implantation is performed with a second resist mask to form a p+ contact region. Thereafter, a heat treatment is used to diffuse and activate the n+ emitter region and the p+ contact region.Type: ApplicationFiled: September 3, 2015Publication date: March 24, 2016Applicant: Fuji Electric Co., Ltd.Inventor: Seiji NOGUCHI
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Patent number: 9166018Abstract: When forming a p+ area and n+ area on the same surface of an n? semiconductor wafer, a first ion implantation forms the p+ area on the entire rear surface of the n? semiconductor wafer. Next, a resist mask selectively covering the rear surface of the n? semiconductor wafer is formed. With this resist mask as the mask, an n-type impurity is injected into the rear surface of the n? semiconductor wafer through a second ion implantation to form the n+ area on a portion deeper from the rear surface of the n? semiconductor wafer than the p+ type area. Thereafter, the n? semiconductor wafer is exposed to an oxygen (O2) gas atmosphere with fluorine (F) gas added to remove the resist mask and a silicon part between the rear surface of the n? semiconductor wafer in an FWD area not covered by the resist mask and the n+ area.Type: GrantFiled: May 9, 2014Date of Patent: October 20, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshihito Kamei, Seiji Noguchi
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Patent number: 9117981Abstract: A silicate phosphor having a coating layer comprising a fluorine-containing compound on its surface which is obtained by a method of heating a mixture of 100 weight parts of a silicate phosphor and 0.5-15 weight parts of ammonium fluoride at a temperature in the range of 200 to 600° C. exhibits high light emission intensity and high moisture resistance.Type: GrantFiled: November 22, 2011Date of Patent: August 25, 2015Assignee: UBE Material Industries, Ltd.Inventors: Kouichi Fukuda, Jin Amagai, Seiji Noguchi, Toru Inagaki, Masaki Tanaka
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Publication number: 20150179638Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.Type: ApplicationFiled: March 9, 2015Publication date: June 25, 2015Inventors: Seiji NOGUCHI, Hidenao KURIBAYASHI
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Patent number: 9023692Abstract: IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n? type semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and n? type drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a p? type spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.Type: GrantFiled: September 12, 2013Date of Patent: May 5, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Souichi Yoshida, Toshihito Kamei, Seiji Noguchi
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Patent number: 9011718Abstract: The emission strength of a light released from a blue light-emitting phosphor having a merwinite crystal structure and an elemental formula of (Sr,Ca)3MgSi2O8 activated with Eu in which a molar ratio of Sr and Ca is in the range of 1:0.10 to 1:0.30 is stable in a wide temperature range.Type: GrantFiled: September 25, 2012Date of Patent: April 21, 2015Assignee: Ube Material Industries, Ltd.Inventors: Kouichi Fukuda, Jin Amagai, Seiji Noguchi, Toru Inagaki, Masaki Tanaka
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Patent number: 8999824Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.Type: GrantFiled: June 11, 2014Date of Patent: April 7, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Seiji Noguchi, Hidenao Kuribayashi
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Publication number: 20140377941Abstract: When forming a p+ area and n+ area on the same surface of an n? semiconductor wafer, a first ion implantation forms the p+ area on the entire rear surface of the n? semiconductor wafer. Next, a resist mask selectively covering the rear surface of the n? semiconductor wafer is formed. With this resist mask as the mask, an n-type impurity is injected into the rear surface of the n? semiconductor wafer through a second ion implantation to form the n+ area on a portion deeper from the rear surface of the n? semiconductor wafer than the p+ type area. Thereafter, the n? semiconductor wafer is exposed to an oxygen (O2) gas atmosphere with fluorine (F) gas added to remove the resist mask and a silicon part between the rear surface of the n? semiconductor wafer in an FWD area not covered by the resist mask and the n+ area.Type: ApplicationFiled: May 9, 2014Publication date: December 25, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Toshihito KAMEI, Seiji NOGUCHI
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Publication number: 20140377942Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.Type: ApplicationFiled: June 11, 2014Publication date: December 25, 2014Inventors: Seiji NOGUCHI, Hidenao KURIBAYASHI