Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.

Abstract: In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

Abstract: The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.

Abstract: A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

Abstract: A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.

Abstract: A semiconductor memory device according to the present invention includes isolations, active regions, control gate electrodes and floating gate electrodes. The isolations are formed on a semiconductor substrate. The active regions are defined on the semiconductor substrate and isolated from each other by the isolations. The control gate electrodes are formed over the semiconductor substrate. Each of the control gate electrodes crosses all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate. Each of the floating gate electrodes is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes.

Abstract: A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

Abstract: A semiconductor memory device according to the present invention includes isolations, active regions, control gate electrodes and floating gate electrodes. The isolations are formed on a semiconductor substrate. The active regions are defined on the semiconductor substrate and isolated from each other by the isolations. The control gate electrodes are formed over the semiconductor substrate. Each of the control gate electrodes crosses all of the isolations and all of the active regions with a first insulating film interposed between the control gate electrode and the semiconductor substrate. Each of the floating gate electrodes is formed for associated one of the active regions so as to cover a side face of associated one of the control gate electrodes with a second insulating film interposed between the floating gate electrode and the control gate electrodes.

Abstract: A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.