Patents by Inventor Seiki Ogura

Seiki Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast program to program verify method
    Patent number: 6628546
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: September 30, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Fast program to program verify method
    Patent number: 6628547
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: September 30, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Nonvolatile semiconductor memory device and method for fabricating the same
    Publication number: 20030173616
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 18, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Fast program to program verify method
    Patent number: 6611461
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: August 26, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Twin MONOS cell fabrication method and array organization
    Publication number: 20030143792
    Abstract: Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 31, 2003
    Applicant: HALO LSI, INC.
    Inventors: Kimihiro Satoh, Seiki Ogura, Tomoya Saito
  • Nonvolatile semiconductor memory device and method for fabricating the same
    Publication number: 20030141540
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Application
    Filed: March 7, 2003
    Publication date: July 31, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Fast program to program verify method
    Publication number: 20030128588
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 10, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Fast program to program verify method
    Publication number: 20030123308
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 3, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Fast program to program verify method
    Publication number: 20030123292
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 3, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Fast program to program verify method
    Publication number: 20030123291
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 3, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Fast program to program verify method
    Publication number: 20030123293
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 3, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Nonvolatile semiconductor memory device and method for fabricating the same
    Publication number: 20030122180
    Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.
    Type: Application
    Filed: February 14, 2003
    Publication date: July 3, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
  • Fast program to program verify method
    Publication number: 20030123290
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: July 3, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Semiconductor memory and method for fabricating the same
    Publication number: 20030116789
    Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.
    Type: Application
    Filed: February 14, 2003
    Publication date: June 26, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Fumihiko Noro, Seiki Ogura
  • Double sidewall short channel split gate flash memory
    Patent number: 6580116
    Abstract: An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: June 17, 2003
    Assignee: Halo LSI, Inc.
    Inventor: Seiki Ogura
  • Data programming implementation for high efficiency CHE injection
    Patent number: 6567314
    Abstract: In the present invention a new method and circuit is disclosed to handle write data during CHE programming for a nonvolatile memory cell including cells created with MONOS technology. A plurality of bit lines are precharged to program inhibit all memory cells coupled to the bit lines. Then a selective bit line is discharged to program the selected memory cell. The number of bit lines selected to be precharged can be reduced to the bit line to be programmed to save power, and precharging a bit line can be done simultaneous with applying program data to a bit line to reduce the number of times a bit line is charged. The number of data latches may be reduced to the actual program data width, resulting in significant area savings and circuit simplification.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: May 20, 2003
    Assignee: Halo Lsi, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura
  • Method for fabricating the control and floating gate electrodes without having their upper surface silicided
    Patent number: 6558997
    Abstract: A semiconductor memory has first and second active regions that have been defined in a semiconductor substrate and electrically isolated from each other. Over the first active region, a control gate electrode has been formed with a control gate insulating film interposed therebetween. A floating gate electrode has been formed adjacent to a side face of the control gate electrode with a capacitive insulating film interposed therebetween. A tunnel insulating film is interposed between the first active region and the floating gate electrode. A gate electrode has been formed over the second active region with a gate insulating film interposed therebetween. Source/drain regions have been defined in respective parts of the second active region beside the gate electrode. Only the source/drain regions and the gate electrode have their upper surface covered with a metal silicide film.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: May 6, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumihiko Noro, Seiki Ogura
  • Fast program to program verify method
    Patent number: 6549463
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: April 15, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Nonvolatile semiconductor memory device and method for fabricating the same
    Patent number: 6545312
    Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: April 8, 2003
    Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.
    Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
  • Process for making and programming and operating a dual-bit multi-level ballistic flash memory
    Patent number: 6542412
    Abstract: A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: April 1, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura