Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film.

Abstract: An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

Abstract: A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Abstract: An integrated circuit using high-performance bipolar and CMOS transistor elements on a single chip is fabricated by a simplified process requiring minimal, if any, changes in the process used for forming either type of device in accordance with a variety of possible device designs. The method according to the invention makes maximal use of self-aligned and self-masking processes to reduce the number of processing steps. The number of processing steps is further reduced by performing some steps concurrently on different device types. Further, the masking steps which are employed are reasonably misregistration tolerant, resulting in high manufacturing yield for the process. Consequently, the process according to the invention substantially eliminates the existence of trade-offs between element performance, integration density and process complexity and cost when plural technologies are integrated on the same chip.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: In this invention a reference circuit is disclosed that produces a reference current to be used in determining the value of data in a flash memory cell. The memory cell current is compared to the reference current in a sense amplifier. A reference circuit that generates the reference current is connect to each bit line of the flash memory and uses bit lines that are not activated when a particular cell is being read to connect the reference current to the sense amplifiers. The use of a reference current allows multi-bit cells to be read by using a variation on the reference circuit that has a plurality of reference transistors creating a plurality of reference currents.. Verification of the programmed and erase states of a flash memory cell can be determined using different values of the reference current that are easily set in the reference circuit by changing a reference voltage.

Abstract: In this invention is described a circuit and method for auto programming of a flash memory cell of an EEPROM. A step split gate is used that has low voltage and low current program conditions. This allows a load device to be connected to each bit line, and sets up a voltage divider between the cell being programmed and the load device. The load device limits the programming current and provides programming data to the cell being programmed. The load device is shut off when the bit line voltage is reduced below a predetermined reference, ending programming of the flash memory cell. The source to drain voltage increases as the memory cell is programmed as a result of the voltage divider between the load device and the cell being programmed thus maintaining pinch off. This produces more energy to program the flash cell and with proper design allows the programming efficiency to be relatively constant over the time that elections are injected onto the floating gate of the flash memory cell.

Abstract: An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.

Abstract: A method of forming EEPROM cells. The method includes forming a tunnel oxide layer on a wafer and forming floating gates on the tunnel oxide layer with the floating gate having sidewalls. Isolation regions may be formed adjacent the sidewalls. A conformal ONO layer of dielectric is formed on the floating gate and sidewalls, using Chemical Vapor Deposition. Next, a selective etch material layer is deposited on the wafer over the conformal dielectric layer. A polish stop layer is deposited on the wafer over the selective etch material layer to define an upper polishing surface above the floating gate. The exposed polish stop layer and underlying selective etch material are removed by depositing an oxide layer on the polish stop layer and then polishing the deposited layer coplanar with the polish stop layer which is an upper polishing surface above the floating gates.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: An improved storage system for use with computers. The system includes a memory array bifurcated into a first and second array segment and a differential sense amplifier configured for selective operation in a first mode establishing one array segment as a reference load and the other array segment as a dynamic load, and a second mode establishing the other array segment as a reference load and the one array segment as a dynamic load. The amplifier senses changes in a parameter in the dynamic load with respect to the reference load.

Abstract: An improved differential sense amplifier for sensing differences in a parameter at a first locus coupled with a first signal source and a second locus coupled with a second signal source. The sensing is effected by a first sensing element coupled with the first locus and a second sensing element coupled with the second locus. The improvement comprises the first sensing element and the second sensing element having differing sensitivities. In the preferred embodiment of the invention, the sensing elements are field effect transistors, and the sensitivity is established by a threshold voltage characteristic. Preferably, the first signal source provides a dynamic signal to be measured and the second signal source provides a reference signal against which the dynamic signal's changes are compared.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: An EEPROM cell capable of being formed at high integration density achieves improved coupling ratio, reduced programming voltage and improved operating margins by provision of a dielectric on lateral sides of the floating gate and a composite control gate electrode structure having conductive sidewalls ohmically connected to a control electrode and overlapping the sides of the floating gate. A methodology for manufacture of this EEPROM cell features a plurality of self-aligned processes producing features of sub-lithographic dimensions.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.