Patents by Inventor Seiyon Kim
Seiyon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160284821Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Applicant: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Publication number: 20160276484Abstract: Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.Type: ApplicationFiled: December 19, 2013Publication date: September 22, 2016Inventors: Seiyon KIM, Rafael RIOS, Fahmida FERDOUSI, Kelin J. KUHN
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Publication number: 20160260802Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: ApplicationFiled: May 16, 2016Publication date: September 8, 2016Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, KELIN J. KUHN, SEIYON KIM, ANAND S. MURTHY, DANIEL B. AUBERTINE
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Publication number: 20160211322Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.Type: ApplicationFiled: October 3, 2013Publication date: July 21, 2016Applicant: INTEL CORPORATIONInventors: Seiyon KIM, Daniel A. SIMON, Nadia M. RAHHAL-ORABI, Chul-Hyun LIM, Kelin J. KUHN
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Patent number: 9385221Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: GrantFiled: April 16, 2015Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Patent number: 9362074Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.Type: GrantFiled: March 14, 2013Date of Patent: June 7, 2016Assignee: Intel CorporationInventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
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Patent number: 9343559Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: GrantFiled: April 20, 2015Date of Patent: May 17, 2016Assignee: INTEL CORPORATIONInventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
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Publication number: 20160086951Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.Type: ApplicationFiled: November 20, 2015Publication date: March 24, 2016Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea, Rafael Rios, Glenn A. Glass
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Publication number: 20160079360Abstract: Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Inventors: Stephen M. Cea, Seiyon Kim, Annalisa Cappellani
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Patent number: 9224808Abstract: Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.Type: GrantFiled: December 23, 2011Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Stephen M. Cea, Seiyon Kim, Annalisa Cappellani
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Patent number: 9224810Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.Type: GrantFiled: December 23, 2011Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea, Rafael Rios, Glenn A. Glass
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Publication number: 20150325648Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Stephen M. CEA, Annalisa CAPPELLANI, Martin D. GILES, Rafael RIOS, Seiyon KIM, Kelin J. KUHN
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Publication number: 20150303258Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Inventors: Kelin J. KUHN, Seiyon KIM, Rafael RIOS, Stephen M. Cea, Martin D. GILES, Annalisa CAPPELLANI, Titash RAKSHIT, Peter CHANG, Willy RACHMADY
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Patent number: 9129829Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.Type: GrantFiled: May 9, 2014Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
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Publication number: 20150228772Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, KELIN J. KUHN, SEIYON KIM, ANAND S. MURTHY, DANIEL B. AUBERTINE
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Publication number: 20150221744Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Applicant: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Patent number: 9087863Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.Type: GrantFiled: December 23, 2011Date of Patent: July 21, 2015Assignee: Intel CorporationInventors: Stephen M. Cea, Annalisa Cappellani, Martin D. Giles, Rafael Rios, Seiyon Kim, Kelin J. Kuhn
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Publication number: 20150179786Abstract: An embodiment concerns selective etching of a structure (e.g., a fin) to form a void with the shape of the original structure. This void then functions as a mold. Flowable dielectric material fills the void to form the same shape as the original structure/mold. Post-processing then occurs (e.g., oxidation build up and annealing) to harden the dielectric in the void. The resulting product is a molded dielectric nanostructure that has the same shape as the original structure but consists of a different material (e.g., dielectric instead of silicon). Other embodiments are described herein.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Inventors: Seiyon Kim, Kelin J. Kuhn
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Patent number: 9064944Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.Type: GrantFiled: March 15, 2013Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
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Publication number: 20150129830Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.Type: ApplicationFiled: March 15, 2013Publication date: May 14, 2015Inventors: Seung Hoon Sung, Kelin Kuhn, Seiyon Kim, Jack Kavalieros, Willy Rachmady