Abstract: A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.

Abstract: In accordance with the development of the fineness of MOSFETs, a gate insulating film and a capacitor insulating film are required to have a smaller thickness and a higher film quality. Accordingly, the present invention is intended to provide a method for forming a high-quality insulating film while preventing hydrogen atoms which cause a leak current and an electron trap from entering the insulating film. The present method uses a gas of molecules containing at least nitrogen, the gas is a compound which includes no oxygen atom and has no bond of a nitrogen atom and a hydrogen atom (N--H) and generates monoatomic nitrogen when the gas dissociates.

Abstract: In a method of forming gate dielectric films, a surface of a Si wafer is first cleaned in an inert gas ambient into a clean state having no naturally oxidized films. Then, after replacing the inert gas ambient with an oxidizing gas containing no nitrogen without exposing the wafer to air, the wafer is heated in the replaced ambient to form a first silicon oxide film on the silicon surface. Then, the ambient is again replaced with an oxidizing gas containing nitrogen, and the wafer is heated in the replaced ambient to form a first oxynitride film between the first silicon oxide film and the silicon. Thereafter, re-oxidation of the wafer is performed in an ambient of oxidizing gas containing no nitrogen to form a second silicon oxide film between the first oxynitride film and the silicon.

Abstract: An insulated-gate field-effect transistor formed in a substrate of a first conductive type or in a well of the first conductive type formed in the substrate is provided. The transistor includes a channel region containing an impurity of the first conductive type; and a source-drain region containing an impurity of a second conductive type. The source-drain region further contains an impurity of the first conductive type; and a concentration of the impurity of the first conductive type contained in the source-drain region is greater than a concentration of the impurity of the first conductive type contained in the channel region but is less than a concentration of the impurity of the second conductive type contained in the source-drain region.

Abstract: A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity dif

Abstract: A method of forming semiconductor devices comprising the steps of forming, by restriction in the increased number of steps by a process close to the normal process, a field effect transistor having a local shallow source/drain diffusion layer on both the sides of a gate electrode for self-matching operation and without etching damages, wherein impurities are ion-implanted onto the semiconductor side wall and onto the substrate surface of both the sides, and thermal treatment operation is effected so as to form the local shallow source/drain diffusing layers by the diffusion for activating the impurities of the deep shallow source drain diffusing layers, thereby to render to be capable of restraining a short channel effect and reducing the parasitic resistance of the semiconductor devices.

Abstract: A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor includes respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

Abstract: A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes of a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor is includes of respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

Abstract: A semiconductor memory device is provided which includes a plurality of memory cells, each of which includes: an active region having an MOS transistor formed in the surface portion of a semiconductor substrate; a gate electrode formed on the substrate for the MOS transistor so as to divide the active region into a source-side active region with a storage contact and a drain-side active region with a bit contact, the portion of the active region which is positioned under the gate electrode functioning as a channel region for the MOS transistor; a first impurity-implanted region formed in a portion of the source-side active region so as to overlap with part of the storage contact and the gate electrode, the portion of the source-side active region which overlaps with the first impurity-implanted region functioning as a source region for the MOS transistor; and a second impurity-implanted region formed in a portion of the drain-side active region so as to overlap with at least one part of the bit contact and th

Abstract: A method of fabricating an insulating gate type field-effect transistor in which a region having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region having a high carrier density, the method comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate; depositing an insulating thin film on the gate electrode and the gate insulating film to a vertical thickness; and performing from above the insulating thin film, ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness of the insulating thin film so as to form the source/drain region; wherein a horizontal thickness of the insulating thin film on opposite sides of the gate electrode is larger than a sum of a lateral diffusion distance of the source/drain region at the time of the ion implantation and a lateral diffusion distance of the source/drain region after the ion implantation.

Abstract: Disclosed is a method of manufacturing semiconductor devices, in which a monocrystalline thin film is formed by dissolving and recrystallizing either amorphous or polycrystalline thin film by annealing with energy beams, comprising the steps of: forming a compound film of a belt-shaped high melting point metal having a width narrower than the diameter of said energy beams and polycrystalline silicon, on said amorphous or polycrystalline thin film; causing said amorphous or polycrystalline thin film to contact with a monocrystalline substrate beneath the center line of said belt-shaped compound film at a position of more than 50 to 200 .mu.

Abstract: A new method of manufacturing semiconductor devices, in which monocrystalline thin film is formed by melting and recrystallizing either amorphous or polycrystalline thin film via annealing by radiation of energy beams, wherein the manufacturing method comprises the formation of a belt-shaped high melting point metal film having a width narrower than the diameter of the radiated energy beams on either an amorphous or polycrystalline thin film and beam scanning in parallel with the belt, by means of radiating energy beams, onto the belt-shaped high melting point metal film, so as to generate a nucleus in a limited area beneath the belt-shaped thin film at the moment the film-covered amorphous or polycrystalline area dissolves recrystallizes so that the said recrystallized area eventually grows into a monocrystalline configuration.