Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

Abstract: Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.

Abstract: A method for manufacturing a semiconductor structure includes: a first mask layer is formed on a dielectric layer, in which a first etching hole extending along a first direction parallel to the dielectric layer is formed in the first mask layer; a side of the first mask layer away from the dielectric layer is planarized; a second mask layer is formed on the first mask layer, in which a second etching hole extending along a second direction parallel to the dielectric layer is formed in the second mask layer, the first etching hole and the second etching hole constitute an etching hole; and the dielectric layer is etched along the etching hole to form the capacitor hole.

Abstract: Methods, systems, and computer programs encoded on a computer storage medium, for training and using machine learning models are disclosed. Methods include creating a model that represents relationships between user attributes, content exposures, and performance levels for a target action using organic exposure data specifying one or more organic exposures experienced by a particular user over a specified time prior to performance of a target action by the particular user and third party exposure data specifying third party exposures of a specified type of digital component to the particular user over the specified time period. Using the model, an incremental performance level attributable to each of the third party exposures at an action time when the target action was performed by the particular user is determined. Transmission criteria for at least some digital components to which the particular user was exposed are modified based on the incremental performance.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: Systems and techniques are described herein for encoding and/or decoding audio information. For example, a process can process an input audio segment to generate a representation of the input audio segment, and can compare the representation of the input audio segment to representations stored in a memory. The representations represent a plurality of audio segments. The process can determine, based on the comparison, target representation(s) of target audio segment(s) from the representations stored in the memory. The process can determine one or more indices associated with the target audio segment(s). The process can then packetize the one or more indices and transmit the one or more packetized indices (e.g., to a decoder configured to decode the packetized indices).

Abstract: A device includes a memory configured to store a collection of sets of weights, each of the sets of weights representing a respective media segment. The device also includes one or more processors configured to generate data representing the detected first input speech segment and to pass the data representing the detected first input speech segment into a collection of memory units. Each memory unit of the collection of memory units includes a set of weights from the collection of sets of weights. The one or more processors are also configured to generate a first estimate of an associated media segment that represents the detected first input speech segment. The associated media segment corresponds to a first memory unit in the collection of memory units.

Abstract: A device includes one or more processors configured to input one or more segments of an input media stream into a feature extractor. The one or more processors are further configured to pass an output of the feature extractor into an utterance classifier to produce at least one representation of at least one utterance class of a plurality of utterance classes. The one or more processors are further configured to pass the output of the feature extractor and the at least one representation into a segment matcher to produce a media output segment identifier.

Abstract: Disclosed is a massive data-driven method for automatically locating a mine microseismic source, including: constructing a microseismic wave calibration data set by using a large-scale seismic data set containing seismic signals and non-seismic signals; constructing a pre-training calibration model based on a full convolution neural network through deep learning of a seismic wave calibration data set; using microseismic data of mine sites for transfer learning of an initial arrival time calibration model to construct an arrival time automatic calibration model suitable for mine microseismic signals; and automatically as well as accurately locating mine microseismic events based on an isokinetic homogeneous isotropic velocity model by using an optimization algorithm to deduce arrival time errors and through repeated iteration and fine-tuning.

Abstract: A manufacturing method of a semiconductor structure is disclosed, which includes: an initial structure is provided; a filling layer covering a spacer is formed on the initial structure; a filling layer with a first preset thickness is removed at a high first etching rate through a first etching process, then a filling layer with a second preset thickness is removed at a low second etching rate through a second etching process, and the partial spacer is exposed; and the filling layer and the spacer are patterned.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.

Abstract: The present disclosure relates to methods, compositions, and kits for treating target nucleic acids, including methods and compositions for fragmenting and tagging nucleic acid (e.g., DNA) using transposome complexes bound to a solid support.

Abstract: Apparatus and methods for a market-based control framework to coordinate a group of autonomous thermostatically controlled loads (TCL) to achieve system-level objectives with pricing incentives is disclosed. In one example of the disclosed technology, a method of providing power to a load via a power grid by submitting bids to a coordinator includes determining an energy response relating price data for one or more energy prices to quantity data for power to be consumed by the load, sending a bid for power for a finite time period based on the energy response to the coordinator, and receiving a clearing price based on: the bid, on bids received from a plurality of additional loads, and a feeder power constraint. In some examples, the energy response is based at least in part on an equivalent thermal parameter model and a control policy indicating one or more power states for the load.

Abstract: Aspects of the disclosure are directed to a data transfer method that can include obtaining a first data packet reported by a first node device; receiving a second data packet forwarded by a signal amplifier, wherein the second data packet is reported by a second node device to the signal amplifier; processing the first data packet and the second data packet to obtain target data information; transferring the target data information to a server.

Abstract: A method for generating a document applet is provided. In the method, an editing interface including an editing region and a component list is displayed. The component list includes a plurality of predefined components. Each of the predefined components is configured to provide a document input template. At least one target component of the plurality of predefined components is added in the editing region. A page of the document applet is generated to include the document input template of each of the at least one target component in the editing region. The document applet is provided to a server. The document applet is configured to perform document processing via the page when downloaded to a user terminal.

Abstract: The present disclosure relates to methods, compositions, and kits for treating target nucleic acids, including methods and compositions for fragmenting and tagging nucleic acid (e.g., DNA) using transposome complexes bound to a solid support.

Abstract: Provided herein are processes for preparing fluorescent 1-cyano-2-substituted isoindole compounds or N-substituted phthalazinium compounds, comprising reacting an aromatic dialdehyde or aromatic aldehyde-ketone compound with a material that contains primary amino or hydrazine groups, and assaying methods involving the processes thereof.

Abstract: The present application provides a method and system for dynamically predicting a deoxynivalenol content of wheat at harvest, including: on the basis of historical data, screening out by particle swarm optimization algorithm combined factors suitable for establishing a prediction model, and establishing the prediction model by using the combined factors; on the basis of data of a current year, predicting a second flowering date and a second harvest date of wheat in the current year by an agricultural model; then obtaining a weather forecast on the basis of the second flowering date and the second harvest date, and combining the weather forecast and geographic data into correlated factors; and finally predicting the deoxynivalenol content of wheat at harvest by means of the prediction model and the correlated factors.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.