Abstract: The present disclosure provides an etching defect detection method, relating to the field of semiconductor technology. The detection method includes: providing a substrate, and sequentially forming a conductive layer and a dielectric layer on the substrate; etching the dielectric layer to form a trench structure; taking the conductive layer as a cathode, and filling the trench structure with an electroplating layer by an electroplating process, to form a product to-be-detected; and testing the product to-be-detected by a defect density detection assembly, to obtain a top-view image of the trench structure, and determining an etching defect of the product to-be-detected according to the top-view image. The etching defect detection method can improve the accuracy of defect identification and prevent a capacitor from failing due to suspension.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate; forming a first mask layer with a first pattern on the stack; forming a first photoresist layer on the first mask layer; exposing the first photoresist layer, and developing to remove the first photoresist layer on the complete die region; and etching the stack by using the first mask layer on the complete die region and the first photoresist layer on the incomplete die region as masks.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: The present application relates to a mask structure, a semiconductor structure and methods for manufacturing the same. The method for manufacturing a mask structure includes: dividing an overall structure into two regions, and developing the array region and the periphery region with a negative photoresist.

Abstract: A method for forming a pattern can include the following operations. A substrate is provided, on the surface of which a patterned photoresist layer is formed. Based on the photoresist layer, isolation sidewalls are formed, in which each isolation sidewall includes a first sidewall close to the photoresist layer and a second sidewall away from the photoresist layer. Core material layers are formed between two adjacent isolation sidewalls. The second sidewalls are removed to form the pattern composed of the first sidewalls and the core material layers.

Abstract: Embodiments provide a method for fabricating an array structure of a columnar capacitor and a semiconductor structure, relating to the field of semiconductor manufacturing technology. In the method, before a mask layer is removed, a thickness of the mask layer in the peripheral region is first adjusted to be equal to a thickness of the mask layer in the array region, thereby avoiding damage to a top support layer caused by different thicknesses of the mask layer. Moreover, in the method, a thickness of the top support layer is increased by means of a supplementary support layer, to increase support strength of the top support layer, thereby further preventing occurrence of tilt of the columnar capacitor due to insufficient support strength of the top support layer.

Abstract: The present application provides a method and system for dynamically predicting a deoxynivalenol content of wheat at harvest, including: on the basis of historical data, screening out by particle swarm optimization algorithm combined factors suitable for establishing a prediction model, and establishing the prediction model by using the combined factors; on the basis of data of a current year, predicting a second flowering date and a second harvest date of wheat in the current year by an agricultural model; then obtaining a weather forecast on the basis of the second flowering date and the second harvest date, and combining the weather forecast and geographic data into correlated factors; and finally predicting the deoxynivalenol content of wheat at harvest by means of the prediction model and the correlated factors.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

Abstract: A method for forming a capacitor array structure includes the following operations. A base is formed, which includes a substrate, a stack structure located on the substrate and a mask layer located on the stack structure in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided. The stack structure is etched along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate. A conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer is formed. The conductive layer and the mask layer at a top surface of the stack structure are removed, and the conductive layer remaining in the capacitor hole forms a lower electrode.

Abstract: A method for generating a document applet is provided. In the method, an editing interface including an editing region and a component list is displayed. The component list includes a plurality of predefined components. Each of the predefined components is configured to provide a document input template. At least one target component of the plurality of predefined components is added in the editing region. A page of the document applet is generated to include the document input template of each of the at least one target component in the editing region. The document applet is provided to a server. The document applet is configured to perform document processing via the page when downloaded to a user terminal.

Abstract: The disclosure discloses an array substrate, a method for manufacturing the same, a display panel and a display device. The array substrate includes a base substrate; a plurality of data lines and a plurality of dummy leads, wherein the plurality of data lines and the plurality of dummy leads are in the same layer on the base substrate, and the plurality of data lines and the plurality of dummy leads extend along the first direction; and at least one dummy lead includes a plurality of wires which extend in the first direction and are disconnected with one another.

Abstract: Provided herein are processes for preparing fluorescent 1-cyano-2-substituted isoindole compounds or N-substituted phthalazinium compounds, comprising reacting an aromatic dialdehyde or aromatic aldehyde-ketone compound with a material that contains primary amino or hydrazine groups, and assaying methods involving the processes thereof.

Abstract: The disclosure provides a method for manufacturing a memory and the memory. The method includes that a laminated structure is formed on a substrate, in which the laminated structure comprises sacrificial layers and supporting layers arranged alternately, a top layer of the laminated structure is a supporting layer, and a supporting layer between two sacrificial layers is provided with intermediate holes filled with a sacrificial material; capacitor holes penetrating through the laminated structure are formed; a first polar plates are formed on the hole walls and the hole bottoms of the capacitor holes; areas corresponding to the intermediate holes in the supporting layer located on the top layer of the laminated structure are removed to form capacitor opening holes, which exposes a sacrificial layer; and all the sacrificial layers and all the sacrificial material are removed through the capacitor opening holes.

Abstract: A data management method is provided. To-be-migrated base data in a first service data set is obtained, mirror data that are same as the base data are generated, and the base data to a second service data set are migrated. Incremental data obtained for the base data are recorded in the migration process of the base data. Adding processing is performed on the mirror data by using the incremental data, and the incremental data are migrated to the second service data set, when the migration process of the base data is completed. The mirror data and the incremental data in the first service data set are cleared when the migration process of the incremental data is completed.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.

Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

Abstract: A method for manufacturing a mask pattern includes the following operations. A pattern transfer layer, an etching stopping layer, a sacrificial layer and a hard mask layer that are stacked from bottom up are formed. The hard mask layer and the sacrificial layer are patterned to obtain sacrificial patterns which expose the etching stopping layer. Side wall structures are formed on the side walls of the sacrificial patterns. The sacrificial patterns are removed. Filling layers are formed between the side wall structures, and the etching selection ratio of the side wall structures to the filling layers is greater than 100. The side wall structures are removed to form an initial mask pattern. The etching stopping layer and the pattern transfer layer are etched based on the initial mask pattern to transfer a pattern of the initial mask pattern to the pattern transfer layer to obtain a target mask pattern.

Abstract: An integrated circuit device includes a storage circuit for storing a canceled value of a key identifier that is associated with a debug key used to sign debugging firmware. A security controller circuit is configurable to reactivate the key identifier to permit the debugging firmware to be loaded to the integrated circuit device to perform debugging functions by changing the canceled value of the key identifier stored in the first storage circuit to a reactivated value.

Abstract: Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.

Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.