Abstract: A method for incremental upgrade is provided. The method is used in a device and includes: receiving an incremental update package corresponding to an application, wherein the incremental update package at least includes an incremental and differential file and the size of a target-version file; obtaining idle resource of a memory in the device and a current-version file corresponding to the application; comparing the idle resource of the memory with a maximum upgrade resource requirement to choose an upgrade process for upgrading the application, wherein the maximum upgrade resource requirement is a capacity sum of the size of the current-version file, the size of the incremental and differential file, and the size of the target-version file; and restoring the target-version file according to the upgrade process, and installing the target-version file.

Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

Abstract: In one embodiment, a technique is provided for automating handover information from project (construction & design) to operation/maintenance. A schema-less repository is defined for holding handover asset objects and governing transformation automation. An information stitching method is defined for multiple-sourced project data integration and incorporating owners' requirement into the repository. A 2-step script-based transformation process is provided to encapsulate information modeling knowledge from a transformation definition.

Abstract: The present invention discloses an unloading device and a self-unloading display device having a first component or a second component cooperatively installed, the first and the second component respectively have a cooperative installation surface, the cooperative installation surface of the first component is provided with at least one unloading device; the unloading device comprises a driving device and a pushing mechanism; the pushing mechanism is connected to a driving device in a transmission way, the pushing mechanism has at least a set of telescopic dowel bars, an end part of the dowel bar is an inclined surface, a small end formed by the inclined surface is arranged close to the cooperative installation surface of the first component; the driving device drives the dowel bar to move along the cooperative installation surface of the first component, the inclined surface of the dowel bar abuts with and moves along the second component.

Abstract: Methods, systems, and computer-readable storage media for providing a table in a database system, the table including a column having a column data type set to an abstract data type, receiving a first data record to be added to the table, the first data record including a first data value to be included in the column, determining a first data type corresponding to a data type of the first data value, changing the column data type from the abstract data type to the first data type, receiving a second data record to be added to the table, the second data record including a second data value to be including in the column, determining a second data type corresponding to the data type of the second data value, and selectively changing the column data type to the second data type.

Abstract: The present invention discloses a guiding device and a self-unloading anti-separation display device for guiding a first component to move on a second component, wherein the first component and the second component respectively have a cooperative installation surface, and at least one of the cooperative installation surface of the first component and the cooperative installation surface of the second component is provided with at least one unloading device; the unloading device has a driving device and a pushing mechanism protruding towards the second component, and the pushing mechanism is butted with the second component to apply a counter force to the first component; the cooperative installation surface of the first component is provided with at least one guidepost; at least one guide hole is arranged at a position of the cooperative installation surface of the second component corresponding to the guidepost; the guidepost is inserted into the guide hole.

Abstract: The present invention discloses a leveling device for adjusting an installation gap between a first component and a second component. The first component and the second component respectively have a cooperative installation surface, the cooperative installation surface of the first component is provided with at least one leveling device; the leveling device comprises a driving device installed in the cooperative installation surface of the first component and an adjustment head rotatably connected to the driving device, the adjustment head moves upwardly or retracts downwardly relative to the cooperative installation surface of the first component; the driving device drives the adjustment head to protrude outside an installation position thereof and abut with the second component located on an opposite side of the installation position of the adjustment head to adjust the gap between the first and second component. The present invention relates to an easy-to-level display screen using the leveling device.

Abstract: A high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10) comprises: a substrate (100); an N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) formed on the substrate (100); and a P-type metal oxide semiconductor field effect transistor (300) formed at a drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200); wherein a gate of the P-type metal oxide semiconductor field effect transistor (300) serves as a gate of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a drain of the P-type metal oxide semiconductor field effect transistor (300) serves as a drain of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) serves as a source of the high voltage P-type lateral double-diffused metal

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

Abstract: Embodiments of the present disclosure relate to a method and device for migrating data. The method comprises identifying cold data in a primary storage system. The method further comprises, in response to determining that the cold data is in a non-compression state, obtaining the cold data from the primary storage system via a first interface, the first interface being configured for a user to access the primary storage system. The method further comprises obtaining, in response to determining the cold data is in a compression state, the cold data in the compression state from the primary storage system via a second interface that is different from the first interface. The method further comprises migrating the obtained cold data from the primary storage system to a secondary storage system.

Abstract: This invention is about a method to make magnetic random access memory with small footprint directly on CMOS VIA with a self-aligned etching process. The process schemes of the method proceeds as: (1) Etch MTJ and BE using one or more of RIE and/or IBE processes with Ta as hard mask; (2) Etch BE using one or more of RIE and/or IBE processes with Ta & sidewall protection layer on MTJ as hard mask; and (3) Etch a part of MTJ and BE using one or more of RIE and/or IBE processes with Ta & sidewall protection layer on top portion of MTJ as hard mask. All the three schemes lead the BE to be self-aligned to MTJ cells, the photo overlay margin is not necessary and circuits could be made extremely small with lower manufacturing cost; The invention also provides schemes to prevent the electrical shorting across the tunnel barrier layer. Through trimming and sidewall protection deposition process, device performance and electrical/magnetic properties could be greatly improved.

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure.

Abstract: An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region (214) formed on the first P well (208); a drain lead-out region (216) formed on the fourth N well (212); a first gate lead-out region formed on surfaces of the second N well (206) and the first P well (208); and a second gate lead-out region formed on surfaces of the first P well (208) and the third N well (210). The first gate lead-out region and the second gate lead-out region are respectively led out by means of metal wires, and then are connected to serve as a gate.

Abstract: The invention features a method for treating patients who have an ALK-driven cancer, which is, or has become, refractory to one or more of crizotinib, CH5424802 and ASP3026, or which bears an ALK mutation identified herein, by administering a compound of formula (I) to the patient. The invention also features methods, kits, and compositions for characterizing ALK-driven cancers to determine whether they express an ALK mutant.

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.