Abstract: A laterally diffused metal oxide semiconductor device and a manufacturing method thereof. The device includes: a substrate of a second conductivity type; a drift region arranged on the substrate and of a first conductivity type; a source region of the first conductivity type; a drain region of the first conductivity type; and a longitudinal floating field plate structure arranged between the source region and the drain region and including a dielectric layer arranged on an inner surface of a trench and polysilicon filling the trench. The trench extends from an upper surface of the drift region downward through the drift region into the substrate. At least two longitudinal floating field plate structures are provided, and at least two of the longitudinal floating field plate structures are located at different positions in a length direction of a conductive channel.

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

Abstract: A battery cell is formed by winding a first electrode plate, a separator, and a second electrode plate, the first electrode plate includes a first current collector, a first active substance layer disposed on a surface of the first current collector, and at least one first tab; the first active substance layer is provided with a first groove, and the first tab is disposed in the first groove and electrically connected to the first current collector; the second electrode plate includes a second current collector, a second active substance layer disposed on a surface of the second current collector, and at least one second tab; and the second tab and the second current collector are integrally formed.

Abstract: The present disclosure provides a multi-party data joint query method, a device, a server and a storage medium. The multi-party data joint query method executed by a manager includes: analyzing a multi-party joint query sentence to obtain a logical execution plan; processing the logical execution plan according to providers of respective nodes in the logical execution plan to obtain a physical execution plan of each provider; and generating a query instruction of each provider according to the physical execution plan of each provider, and sending the query instruction to respective provider. The query instruction is configured to instruct the providers to perform a query cooperatively.

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

Abstract: A method, an apparatus, and a server for managing an image across cloud servers relate to the field of computer technologies. The method includes: obtaining layered image information of a layered image file of a service virtual machine on a second cloud server; creating a boot partition and a rootfs partition based on a pre-created installer virtual machine and the layered image information; and creating, based on the boot partition and the rootfs partition, an image corresponding to the service virtual machine. In this method, no manual operation is required, and not only reducing management costs, but also improving management efficiency.

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

Abstract: A target positioning device and method based on a plecotus auritus double-pinna bionic sonar. An echo positioning device based on bionic pinnae of a bat can determine an azimuth and an elevation of a target to locate the spatial location of the target by using echoes obtained by two array elements, resolving a problem that two array element antennas cannot locate the space coordinates. In a positioning method based on bionic pinnae of a bat according to filtering characteristics of bat ears, a method for estimating a spatial location by a neural network is used, and a pulse string estimation method is used to reduce the error of estimated angles, to obtain a precise azimuth and elevation.

Abstract: A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Abstract: This application relates to the field of cloud computing, and specifically, to a method for providing an edge service for a terminal by using a resource of an edge resource cluster in a cloud computing system. The cloud computing system includes a central resource cluster and at least one edge resource cluster. The method includes: a management node deployed in the central resource cluster determines a target execution node based on an edge service application range that is specified by a tenant or that is determined by the management node based on information about a tenant; the target execution node determines, according to an edge service policy sent by the management node, a target edge node from at least one edge node deployed in the at least one edge resource cluster; and the target execution node further forwards an edge service request to the target edge node.

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

Abstract: A communication method, a communications apparatus, and a storage medium are disclosed, to reduce a probability that consecutive bit errors occur in a communications system. A received to-be-sent signal is modulated to obtain a modulated signal, and N rounds of operations are further performed on the modulated signal to obtain an encoded signal. An output of the 1st-round operation in the N rounds of operations is determined based on the modulated signal and an output that is of the Nth-round operation and that is processed by a first delay circuit, and an output of the ith-round operation in the N rounds of operations is determined based on an output of the (i?1)th-round operation and an output that is of the Nth-round operation and that is processed by a second delay circuit, where i is an integer greater than 1 and less than or equal to N.

Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.