Patents by Inventor Seok Ho Kim
Seok Ho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11283235Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.Type: GrantFiled: August 12, 2019Date of Patent: March 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hoe-Chul Kim, Hoon-Joo Na
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Publication number: 20200373186Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.Type: ApplicationFiled: December 4, 2019Publication date: November 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
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Patent number: 10770447Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.Type: GrantFiled: May 1, 2019Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
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Patent number: 10763243Abstract: A substrate bonding apparatus and a method of bonding substrates, the apparatus including an upper chuck securing a first substrate onto a lower surface thereof such that the first substrate is downwardly deformed into a concave surface profile; a lower chuck arranged under the upper chuck and securing a second substrate onto an upper surface thereof such that the second substrate is upwardly deformed into a convex surface profile; and a chuck controller controlling the upper chuck and the lower chuck to secure the first substrate and the second substrate, respectively, and generating a shape parameter for changing a shape of the second substrate to the convex surface profile from a flat surface profile.Type: GrantFiled: September 19, 2018Date of Patent: September 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-Hyung Kim, Sung-Hyup Kim, Kyeong-Bin Lim, Seok-Ho Kim, Tae-Yeong Kim
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Publication number: 20200168471Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane regionType: ApplicationFiled: June 12, 2019Publication date: May 28, 2020Inventors: JOO HEE JANG, Seok Ho Kim, Hoon Joo NA, Kwang Jin Moon, Jae Hyung Park, Kyu Ha Lee
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Publication number: 20200148786Abstract: The present invention relates to a fusion protein for cancer treatment and a use thereof. The fusion protein for preventing or treating cancer of the present invention comprises a fusion polypeptide comprising: an antibody or fragment thereof binding to a tumor-associated antigen; a linker; and a NK cell-inducing protein of CXCL16, wherein a co-administration of the fusion polypeptide along with the NK cells, an immunocyte therapeutic agent, greatly increases an influx of the NK cells into cancer expressing a certain antigen, thereby having a remarkable effect on preventing or treating cancer.Type: ApplicationFiled: April 5, 2018Publication date: May 14, 2020Inventors: Seok Ho Kim, Jaemin Lee, Duck Cho
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Patent number: 10639875Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.Type: GrantFiled: December 18, 2017Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-yeong Kim, Pil-kyu Kang, Seok-ho Kim, Kwang-jin Moon, Na-ein Lee, Ho-jin Lee
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Publication number: 20200136341Abstract: A semiconductor laser device may include a first cladding on a substrate, an optical waveguide on the first cladding, a laser light source chip on the optical waveguide to generate a laser beam, a first adhesive layer between the optical waveguide and the laser light source chip, and a second adhesive layer covering a sidewall of the laser light source chip.Type: ApplicationFiled: August 12, 2019Publication date: April 30, 2020Inventors: Pil-Kyu KANG, Seok-Ho KIM, Tae-Yeong KIM, Hoe-Chul KIM, Hoon-Joo NA
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Patent number: 10468400Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.Type: GrantFiled: January 12, 2018Date of Patent: November 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pil Kyu Kang, Seok Ho Kim, Tae Yeong Kim, Kwang Jin Moon, Ho Jin Lee
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Publication number: 20190259744Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Ho Jin LEE, Seok Ho KIM, Kwang Jin MOON, Byung Lyul PARK, Nae In LEE
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Publication number: 20190189593Abstract: A substrate bonding apparatus and a method of bonding substrates, the apparatus including an upper chuck securing a first substrate onto a lower surface thereof such that the first substrate is downwardly deformed into a concave surface profile; a lower chuck arranged under the upper chuck and securing a second substrate onto an upper surface thereof such that the second substrate is upwardly deformed into a convex surface profile; and a chuck controller controlling the upper chuck and the lower chuck to secure the first substrate and the second substrate, respectively, and generating a shape parameter for changing a shape of the second substrate to the convex surface profile from a flat surface profile.Type: ApplicationFiled: September 19, 2018Publication date: June 20, 2019Inventors: Jun-Hyung KIM, Sung-Hyup KIM, Kyeong-Bin LIM, Seok-Ho KIM, Tae-Yeong KIM
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Patent number: 10325897Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.Type: GrantFiled: September 15, 2017Date of Patent: June 18, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Jin Lee, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
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Publication number: 20180370210Abstract: Provided are a wafer bonding apparatus for accurately detecting a bonding state of wafers in a wafer bonding process and/or in a wafer bonding system including the wafer bonding apparatus. The wafer bonding apparatus includes a first supporting plate including a first surface and vacuum grooves for vacuum-absorption of a first wafer disposed on the first surface, a second supporting plate including a second surface facing the first surface. A second wafer is on the second surface. The wafer bonding apparatus and/or the wafer bonding system include a bonding initiator at a center portion of the first supporting plate, and an area sensor on the first supporting plate and configured to detect a propagation state of bonding between the first wafer and the second wafer.Type: ApplicationFiled: December 18, 2017Publication date: December 27, 2018Inventors: Tae-yeong Kim, Pil-kyu Kang, Seok-ho Kim, Kwang-jin Moon, Na-ein Lee, Ho-jin Lee
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Publication number: 20180226390Abstract: A method of manufacturing a substrate structure includes providing a first substrate including a first device region on a first surface, providing a second substrate including a second device region on a second surface, such that a width of the first device region is greater than a width of the second device region, and bonding the first substrate and the second substrate, such that the first and second device regions are facing each other and are electrically connected to each other.Type: ApplicationFiled: January 12, 2018Publication date: August 9, 2018Inventors: Pil Kyu KANG, Seok Ho KIM, Tae Yeong KIM, Kwang Jin MOON, Ho Jin LEE
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Publication number: 20180138164Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.Type: ApplicationFiled: September 15, 2017Publication date: May 17, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Ho Jin LEE, Seok Ho Kim, Kwang Jin Moon, Byung Lyul Park, Nae In Lee
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Patent number: 9941243Abstract: A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.Type: GrantFiled: January 24, 2017Date of Patent: April 10, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-yeong Kim, Pil-kyu Kang, Seok-ho Kim, Kwang-jin Moon, Ho-jin Lee
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Patent number: 9935298Abstract: Disclosed herein is a battery cell case. The battery cell case includes a front case plate and a rear case plate which are separably coupled to each other. The structures of the front and rear case plates are symmetrical structures, so that the battery cell case can be easily assembled in such a way that the front and rear case plates are coupled to each other with the battery cell disposed therebetween and are fastened to each other by holders fitted over the opposite ends of the case plates. In another embodiment, the structures of the front and rear case plates may be asymmetrical structures so that the front and rear case plates can be coupled with each other in an insert coupling manner without using a separate tool or fastening means.Type: GrantFiled: September 9, 2015Date of Patent: April 3, 2018Assignee: Global Battery Co., Ltd.Inventors: Gueng Hyun Nam, Seok Ho Kim, Min Ho Jang, Dae Ung Kim
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Patent number: 9935037Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.Type: GrantFiled: January 18, 2017Date of Patent: April 3, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pil-kyu Kang, Ho-jin Lee, Byung-lyul Park, Tae-yeong Kim, Seok-ho Kim
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Patent number: 9930211Abstract: An apparatus includes a main body having a stage on which an object to be scanned is supported; a camera module that acquires partial images by photographing a part of the object to be scanned; a rotational body in which the camera module is installed and which is rotatably provided; a driving unit that controls a rotational motion of the rotational body; and an image processing unit that forms a synthesized image by synthesizing the partial images acquired by the camera module, the apparatus capable of acquiring an image with high resolution.Type: GrantFiled: October 24, 2016Date of Patent: March 27, 2018Assignee: S-PRINTING SOLUTION CO., LTD.Inventors: Byung Jun Sung, Sung Hyun Yoon, Seok Ho Kim
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Patent number: 9865581Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.Type: GrantFiled: November 13, 2015Date of Patent: January 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Hee Jang, Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Jum-Yong Park, Jin-Ho An, Kyu-Ha Lee, Yi-Koan Hong