Patents by Inventor Seok-Jun Won

Seok-Jun Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786785
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kook-Tae Kim, Young-Tak Kim, Ho-Sung Son, Seok-Jun Won, Ji-Hye Yi, Chul-Woong Lee
  • Patent number: 9702041
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 11, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Patent number: 9580800
    Abstract: A method for operating semiconductor manufacturing equipment is provided. The method includes forming a conductive thin film on an inner side surface of a reaction chamber and on a substrate in the reaction chamber, the conductive thin film including a first conductive material, and forming a particle preventive layer on the inner side surface of the reaction chamber in which the conductive thin film is formed.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Hoon Lee, June-Hee Lee, Geun-Woo Kim, Min-Woo Song, Seok-Jun Won
  • Patent number: 9583592
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pan-Kwi Park, Dong-Suk Shin, Seok-Jun Won, Weon-Hong Kim, Jae-Gon Lee
  • Patent number: 9553094
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-Hsiung Tseng, Ju-Youn Kim, Seok-Jun Won, Jong-Ho Lee, Hye-Lan Lee, Yong-Ho Ha
  • Publication number: 20160315087
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Application
    Filed: March 14, 2016
    Publication date: October 27, 2016
    Inventors: Wei-Hsiung TSENG, Ju-Youn KIM, Seok-Jun WON, Jong-Ho LEE, Hye-Lan LEE, Yong-Ho HA
  • Publication number: 20160281234
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
    Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
  • Patent number: 9431515
    Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming an insulating layer that includes a trench therein. The method includes forming a high-k layer in the trench. Moreover, the method includes forming a metal layer on the high-k layer, then performing a first heat treatment at a first temperature, and performing a second heat treatment at a second temperature that is higher than the first temperature.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Weon-Hong Kim, Moon-Kyun Song
  • Patent number: 9406502
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: August 2, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Publication number: 20160211378
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Kook-Tae KIM, Young-Tak KIM, Ho-Sung SON, Seok-Jun WON, Ji-Hye YI, Chul-Woong LEE
  • Patent number: 9312376
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kook-Tae Kim, Young-Tak Kim, Ho-Sung Son, Seok-Jun Won, Ji-Hye Yi, Chul-Woong Lee
  • Publication number: 20160093617
    Abstract: A semiconductor device, including a substrate; an interlayer insulating layer having a trench on the substrate, the trench having a bottom and sidewalls; a dielectric layer on the bottom and sidewalls of the trench; a work function control layer on the dielectric layer; a wetting layer on the work function control layer; a gap fill layer on the wetting layer; and a reactive layer between the wetting layer and the gap fill layer, the reactive layer being thicker than the gap fill layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 31, 2016
    Inventors: Jung-Min PARK, Suk-Hoon KIM, Min-Woo SONG, Seok-Jun WON, In-Hee LEE, Kyung-Il HONG, Sang-Jin HYUN
  • Patent number: 9287181
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-Hsiung Tseng, Ju-Youn Kim, Seok-Jun Won, Jong-Ho Lee, Hye-Lan Lee, Yong-Ho Ha
  • Patent number: 9275993
    Abstract: A semiconductor device includes a first interface film on a first area of a substrate, the first interface film including a first growth interface film and a second growth interface film on a lower portion of the first growth interface film, a first dielectric film on the first interface film, and a first gate electrode on the first dielectric film.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Moon-Kyun Song, Seok-Jun Won
  • Publication number: 20160035861
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.
    Type: Application
    Filed: April 27, 2015
    Publication date: February 4, 2016
    Inventors: PAN-KWI PARK, DONG-SUK SHIN, SEOK-JUN WON, WEON-HONG KIM, JAE-GON LEE
  • Publication number: 20160013107
    Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming an insulating layer that includes a trench therein. The method includes forming a high-k layer in the trench. Moreover, the method includes forming a metal layer on the high-k layer, then performing a first heat treatment at a first temperature, and performing a second heat treatment at a second temperature that is higher than the first temperature.
    Type: Application
    Filed: March 6, 2015
    Publication date: January 14, 2016
    Inventors: Seok-Jun Won, Weon-Hong Kim, Moon-Kyun Song
  • Patent number: 9218977
    Abstract: A fabricating method of a semiconductor device includes stacking a high-k dielectric film not containing silicon (Si) and an insulating film containing silicon (Si) on a substrate, and diffusing Si contained in the insulating film into the high-k dielectric film by annealing the substrate having the high-k dielectric film and the insulating film stacked thereon.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Jun Won, Weon-Hong Kim, Moon-Kyun Song, Hyung-Suk Jung
  • Publication number: 20150270177
    Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.
    Type: Application
    Filed: January 8, 2015
    Publication date: September 24, 2015
    Inventors: Wei-Hsiung TSENG, Ju-Youn KIM, Seok-Jun WON, Jong-Ho LEE, Hye-Lan LEE, Yong-Ho HA
  • Publication number: 20150252470
    Abstract: A method for operating semiconductor manufacturing equipment is provided. The method includes forming a conductive thin film on an inner side surface of a reaction chamber and on a substrate in the reaction chamber, the conductive thin film including a first conductive material, and forming a particle preventive layer on the inner side surface of the reaction chamber in which the conductive thin film is formed.
    Type: Application
    Filed: January 20, 2015
    Publication date: September 10, 2015
    Inventors: BYOUNG-HOON LEE, JUNE-HEE LEE, GEUN-WOO KIM, MIN-WOO SONG, SEOK-JUN WON
  • Publication number: 20150221497
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Applicants: GENITECH, INC., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM