Patents by Inventor Seok-Jun Won

Seok-Jun Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7807584
    Abstract: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually. One of the metallic source gases may include an amino-group or an alkoxy-group and another metallic source gas may include neither an amino-group nor an alkoxy-group. A plasma may be produced in the reactor from the reactant gas.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: October 5, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-youn Kim, Seok-jun Won, Weon-hong Kim, Min-woo Song, Jung-min Park
  • Publication number: 20100170441
    Abstract: In a method and an apparatus for forming metal oxide on a substrate, a source gas including metal precursor flows along a surface of the substrate to form a metal precursor layer on the substrate. An oxidizing gas including ozone flows along a surface of the metal precursor layer to oxidize the metal precursor layer so that the metal oxide is formed on the substrate. A radio frequency power is applied to the oxidizing gas flowing along the surface of the metal precursor layer to accelerate a reaction between the metal precursor layer and the oxidizing gas. Acceleration of the oxidation reaction may improve electrical characteristics and uniformity of the metal oxide.
    Type: Application
    Filed: March 23, 2010
    Publication date: July 8, 2010
    Inventors: Seok-Jun Won, Yong-Min Yoo, Min-Woo Song, Dae-Youn Kim, Young-Hoon Kim, Weon-Hong Kim, Jung-Min Park, Sun-Mi Song
  • Patent number: 7732296
    Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corres
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-min Park, Seok-jun Won, Min-woo Song, Yong-kuk Jeong, Dae-jin Kwon, Weon-hong Kim
  • Patent number: 7708969
    Abstract: In a method and an apparatus for forming metal oxide on a substrate, a source gas including metal precursor flows along a surface of the substrate to form a metal precursor layer on the substrate. An oxidizing gas including ozone flows along a surface of the metal precursor layer to oxidize the metal precursor layer so that the metal oxide is formed on the substrate. A radio frequency power is applied to the oxidizing gas flowing along the surface of the metal precursor layer to accelerate a reaction between the metal precursor layer and the oxidizing gas. Acceleration of the oxidation reaction may improve electrical characteristics and uniformity of the metal oxide.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Yong-Min Yoo, Min-Woo Song, Dae-Youn Kim, Young-Hoon Kim, Weon-Hong Kim, Jung-Min Park, Sun-Mi Song
  • Patent number: 7700454
    Abstract: A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-don Kim, Jae-hyun Joo, Seok-jun Won, Jung-hee Chung, Jin-yong Kim, Suk-jin Chung
  • Patent number: 7679124
    Abstract: An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: March 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kuk Jeong, Seok-jun Won, Dae-jin Kwon, Min-woo Song, Weon-hong Kim
  • Patent number: 7633112
    Abstract: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: December 15, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Jung-min Park
  • Patent number: 7623338
    Abstract: In a device including multiple metal-insulator-metal (MIM) capacitors and a method of fabricating the same, the multiple MIM capacitors comprise a lower interconnect in a substrate; a first dielectric layer on the lower interconnect; a first intermediate electrode pattern on the first dielectric layer overlapping with the lower interconnect; a second intermediate electrode pattern on the first dielectric layer and spaced apart from the first intermediate electrode pattern in a same plane of the device as the first intermediate electrode pattern; a second dielectric pattern on the second intermediate electrode pattern; and an upper electrode pattern on the second dielectric pattern.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-jun Won
  • Patent number: 7612399
    Abstract: A semiconductor integrated circuit device includes a first interlayer insulation film having a contact therein. The contact has an upper surface and including a void therein having an open upper portion. The device further includes a plasma damage reduction unit including a lower electrode conformably on the void of the contact and on the upper surface of the contact, a dielectric film on the lower electrode, and an upper electrode on the dielectric film. The thickness of the portion of the dielectric film in the void is smaller than the thickness of the portion of the dielectric film on the upper surface of the contact.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: November 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Min-Woo Song, Weon-Hong Kim
  • Patent number: 7581550
    Abstract: A method of cleaning a reaction chamber using a substrate having a metal catalyst thereon is disclosed. The method includes preparing a substrate having a catalyst layer to activate a cleaning gas. The substrate is introduced into the reaction chamber. Next, a cleaning gas is introduced into the reaction chamber. Contaminations in the reaction chamber are exhausted. The substrate having a metal catalyst layer is also disclosed.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Weon-Hong Kim, Min-Woo Song
  • Patent number: 7563672
    Abstract: Integrated circuit devices including metal-insulator-metal (MIM) capacitors are provided. The MIM capacitors may include an upper electrode having first and second layers. The first layer of the upper electrode includes a physical vapor deposition (PVD) upper electrode and the second layer of the upper electrode includes an ionized PVD (IPVD) upper electrode on the PVD upper electrode. Related methods are also provided.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: July 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Jin Kwon, Jung-Min Park, Seok-Jun Won, Min-Woo Song, Weon-hong Kim, Ju-youn Kim
  • Patent number: 7554146
    Abstract: In a metal-insulator-metal (MIM) capacitor and a method of fabricating the MIM capacitor, a metal-insulator-metal (MIM) capacitor comprises: a lower electrode pattern which is formed on a substrate and includes a conductive layer having a portion as a lower interconnect; a dielectric layer on the lower electrode pattern; a first upper electrode pattern on the dielectric layer; an interlayer insulating layer which covers the first upper electrode pattern, the dielectric layer, and the lower electrode pattern and has a planarized upper surface; a second upper electrode opening pattern formed in the interlayer insulating layer to expose the first upper electrode pattern; a second upper electrode which fills the opening pattern and has an upper surface that is substantially level with an upper surface of the interlayer insulating layer; and an upper interconnect on the interlayer insulating layer and contacts the second upper electrode.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 30, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Dae-jin Kwon
  • Patent number: 7508649
    Abstract: Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: March 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-jin Kwon, Seok-jun Won, Weon-hong Kim, Yong-kuk Jeong, Min-woo Song, Jung-min Park
  • Publication number: 20090045391
    Abstract: Provided is a switch device that can be reliably turned on or off using a nanostructure that includes a nanotube and/or a nanowire. The switch device includes a lower conductive film formed on a substrate, a first insulating film formed on the lower conductive film and having a first hole that exposes at least a portion of the first lower conductive film, and a conductive film spacer formed on an inner wall of the first hole of the first insulating film. A switch device may include a nanostructure having an end electrically connected to the lower conductive film, including a nanotube and/or a nanowire, extending substantially vertically from the lower conductive film and penetrating through the first hole, and separated from the conductive film spacer with a working gap interposed therebetween.
    Type: Application
    Filed: June 4, 2008
    Publication date: February 19, 2009
    Inventor: Seok-Jun Won
  • Patent number: 7491654
    Abstract: Example embodiments of the present invention relate to a method of forming a dielectric thin film and a method of fabricating a semiconductor memory device having the same. Other example embodiments of the present invention relate to a method of forming a ZrO2 thin film and a method of fabricating a capacitor of a semiconductor memory device using the ZrO2 thin film as a dielectric layer. A method of forming a ZrO2 thin film may include supplying a zirconium precursor on a substrate maintained at a desired temperature, thereby forming a chemisorption layer of the precursor on the substrate. The zirconium precursor may be a tris(N-ethyl-N-methylamino)(tert-butoxy) zirconium precursor. The substrate having the chemisorption layer of the precursor may be exposed to the plasma atmosphere of oxygen-containing gas for a desired time, thereby forming a Zr oxide layer on the substrate, and a method of fabricating a capacitor of a semiconductor memory device having the ZrO2 thin film.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Woo Song, Seok-Jun Won, Weon-Hong Kim, Dae-Jin Kwon, Jung-Min Park
  • Patent number: 7481882
    Abstract: A method for forming a film includes forming the film on a substrate, followed by performing a first annealing of the film at a temperature lower than a crystallization temperature of the film. A second annealing of the film is performed at a temperature higher that the crystallization temperature. Forming the film and the first annealing of the film are performed in situ in a chamber. Alternatively, the first and second annealing are performed in situ in an apparatus.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jun Won, Young-wook Park, Yong-woo Hyung
  • Patent number: 7476922
    Abstract: A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: January 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Jun Won, Yong-Kuk Jeong, Dae-Jin Kwon, Min-Woo Song, Weon-Hong Kim
  • Publication number: 20090001437
    Abstract: An integrated circuit device may include a first insulating layer on a substrate with an opening through the first insulating layer. A conductive layer may be on the first insulating layer with the first insulating layer between the conductive layer and the substrate and with the conductive layer set back from the opening. A second insulating layer may be on the conductive layer with the conductive layer between the first and second insulating layers. The second insulating layer may be set back from the opening, and a sidewall of the conductive layer adjacent the opening may be recessed relative to a sidewall of the second insulating layer adjacent the opening. An insulating spacer on portions of the first insulating layer may surround the opening, and the insulating spacer may be on the sidewall of the second insulating layer adjacent the opening so that the insulating spacer is between the sidewall of the second conductive layer and the opening.
    Type: Application
    Filed: June 19, 2008
    Publication date: January 1, 2009
    Inventors: Seok-Jun Won, Jung-Min Park
  • Publication number: 20080283905
    Abstract: Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second regions having a lower density of charge-trap sites than the first region, and a gate electrode on the charge-trap insulation layer, wherein the first region is overlapped by the gate electrode and the second regions are outside of the first region.
    Type: Application
    Filed: April 11, 2008
    Publication date: November 20, 2008
    Inventor: Seok-Jun Won
  • Publication number: 20080265371
    Abstract: A capacitor unit includes a first capacitor and a second capacitor. The first capacitor includes a first lower electrode, a first dielectric layer pattern and a first upper electrode sequentially stacked. The first capacitor includes a first control layer pattern for controlling a voltage coefficient of capacitance (VCC) of the first capacitor between the first lower electrode and the first dielectric layer pattern. The second capacitor includes a second lower electrode, a second dielectric layer pattern and a second upper electrode sequentially stacked. The second lower electrode is electrically connected to the first upper electrode, and the second upper electrode is electrically connected to the second lower electrode. The second capacitor includes a second control layer pattern for controlling a VCC of the second capacitor between the second lower electrode and the second dielectric layer pattern.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 30, 2008
    Inventors: Jung-Min Park, Seok-Jun Won, Min-Woo Song, Weon-Hong Kim