Abstract: A method of controlling the gait of a wearable robot using foot sensors of the robot. Whether or not the robot is walking is determined. When the robot is walking, whether the robot is supported on both feet or one foot using the foot sensors is determined. When the robot is walking and is supported on both feet, posture-maintaining control is carried out. When the robot is walking and is supported on one foot, support control is carried out over a supporting leg based on gravity compensation and load compensation. When the robot is walking and is supported on one foot, an imaginary repulsive force by which a swinging leg swings is generated.

Abstract: According to example embodiments, a variable resistance memory device may include memory cells, in which contact areas between word lines and a variable resistance layer are almost constant. The variable resistance memory device may include a vertical electrode on a substrate, horizontal electrode layers and insulating layers sequentially and alternately stacked on the substrate. The horizontal electrode layers and the insulating layers may be adjacent to the vertical electrode. The variable resistance layer may be between the vertical electrode the horizontal electrode layers. A thickness of one of the horizontal electrode layers adjacent to the substrate may be thickness than a thickness of an other of the horizontal electrode layers that is spaced apart from the substrate.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.

Abstract: To manufacture a stack semiconductor package, a board mold covers a first semiconductor. The board mold includes a first face and a second face opposite to the first face. An active surface of the first semiconductor faces the second face. A first opening is formed in the board mold from the second surface. The first opening is disposed on the first semiconductor. A second opening penetrates the board mold from the first surface. A conductive metal layer fills the first and the second openings using an electroless plating method. A plurality of semiconductor devices is stacked on the first face of the board mold.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.

Abstract: According to example embodiments, a variable resistance memory device may include memory cells, in which contact areas between word lines and a variable resistance layer are almost constant. The variable resistance memory device may include a vertical electrode on a substrate, horizontal electrode layers and insulating layers sequentially and alternately stacked on the substrate. The horizontal electrode layers and the insulating layers may be adjacent to the vertical electrode. The variable resistance layer may be between the vertical electrode the horizontal electrode layers. A thickness of one of the horizontal electrode layers adjacent to the substrate may be thickness than a thickness of an other of the horizontal electrode layers that is spaced apart from the substrate.

Abstract: A main hub, a sub hub, and a sensor node communicating in a wireless body area network (WBAN) including at least one sub hub, and a communication method thereof, are provided. A communication method of the main hub, includes assigning a beacon slot to the sub hub. The method further includes receiving, from the sub hub, a beacon signal based on the beacon slot. The method further includes verifying whether the sub hub includes data to be transmitted to the main hub based on the beacon signal. The method further includes receiving, from the sub hub, the data based on a result of the verification.

Abstract: A system for controlling driving of a wearable robot may include a drive unit for operating a drive joint of the robot, a measurement unit for measuring an actual angle and an actual angular velocity of the drive joint in the robot, a sensing unit for determining a human torque applied by a wearing user to the drive joint, and a control unit for determining a target angular velocity of the robot by applying the determined human torque to an admittance model and for determining a required torque that may be input to the drive unit of the robot by applying an optimal control gain to a difference between the target angular velocity and the actual angular velocity of the robot.

Abstract: A system for simulating interdependencies between multiple critical physical infrastructure models includes a first infrastructure data model that models a first physical infrastructure; a second infrastructure data model that models a second physical infrastructure, wherein the second physical infrastructure is a different physical infrastructure from the first physical infrastructure; a simulation engine adapted to automatically produce a change in the second infrastructure data model in response to a change in the first infrastructure data model; a user interface permitting a user to interact with the simulation engine; wherein the user interface and the simulation engine are configured such that the user can disable an element of the first physical infrastructure, and subsequently re-enable the element of the first physical infrastructure; wherein the first infrastructure data model comprises a transport network; and wherein the second infrastructure data model comprises a channel network.

Abstract: Disclosed is an apparatus for extracting a drive characteristic of a drive system. The apparatus includes a drive unit supplying a rotating force to a drive shaft. A force-torque sensor unit is detachably coupled to the drive shaft of the drive unit, and may not rotate when it is coupled to the drive shaft. A load unit is detachably coupled to the drive shaft of the drive unit. A control unit is configured to control drive energy supplied to the drive unit, derive a drive-unit constant by using a relation between the input drive energy and measurement torque when the drive unit is coupled to the force-torque sensor unit, calculate frictional torque using the derived drive-unit constant, the input drive energy, an inertia moment and angular acceleration of the load unit when the drive unit is coupled to the load unit, and derive a frictional coefficient from the frictional torque.

Abstract: Disclosed is a module for measuring repulsive force for a walking robot. More specifically the module includes a base frame and plurality of installation units provided on the base frame and surrounded by a plurality of side surfaces configured as inclined surfaces having a predetermined angle and a top surface formed in a horizontal plane. The module also includes a 1-axis force sensor provided on each side surface and the top surface of the installation unit. A control unit calculates a sum force of the respective installation units from measurement data of the force sensor and calculates the ground reaction force (GRF) by integrating the sum force of the respective installation units.

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract: The present invention relates to methods and compositions for diagnosing SIRS, sepsis, severe sepsis, septic shock, or MODS in a subject, or assigning a prognostic risk for one or more clinical outcomes for a subject suffering from SIRS, sepsis, severe sepsis, septic shock, or MODS, the method comprising performing an immunoassay for CCL23 splice variant.

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract: The present invention relates to methods for the diagnosis and evaluation of BNP-related diseases. In particular, patient test samples are analyzed for the presence and amount of a plurality of natriuretic peptides, and a combined natriuretic peptide result is used as a diagnostic marker.

Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract: An image sensor package assembling method includes providing a substrate on which a plurality of image sensors are mounted; providing a housing strip having a plurality of housings arranged corresponding to an arrangement of the image sensors on the substrate, each of the housings having an aperture corresponding to an active surface of the corresponding image sensor and a cavity enclosing an edge of the corresponding image sensor; attaching a transparent cover plate sealing the apertures of the housings on the housing strip after attaching the housing strip on the substrate; and separating image sensor packages from each other by successively cutting the transparent cover, the housing strip and the substrate. Increased yield and production efficiency can be realized.