Abstract: Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.

Abstract: A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.

Abstract: The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.

Abstract: Embodiments provide a digital RF receiver including a signal converting unit which converts an RF signal received from an external device into a digital signal, a plurality of functional modules which processes the digital signal in accordance with a predetermined algorithm when the digital signal is input, and a signal processing controller which selects at least one of the plurality of functional modules to control the digital signal to be processed in consideration of whether an IF signal component is included in the digital signal or a sampling rate related with sampling information of the digital signal.

Abstract: The inventive concept relates to a wireless communication receiver. The wireless communication receiver includes a second off-chip RF filter, an RF-to-digital converter and a digital pre-processor processing a signal converted into a digital. The RF-to-digital converter converts an RF signal being received into a digital signal of DC frequency band or intermediate frequency band and has a dynamic range that can process a wanted RF band signal and unwanted signals near to the wanted RF band signal. The digital pre-processor digitally controls a signal gain to transmit it to a modulator/demodulator.

Abstract: Embodiments provide a digital RF receiver including a signal converting unit which converts an RF signal received from an external device into a digital signal, a plurality of functional modules which processes the digital signal in accordance with a predetermined algorithm when the digital signal is input, and a signal processing controller which selects at least one of the plurality of functional modules to control the digital signal to be processed in consideration of whether an IF signal component is included in the digital signal or a sampling rate related with sampling information of the digital signal.

Abstract: Provided is a frequency selective noise canceller including: a frequency selective single to differential converter having a band pass filter function, converting a received single input signal into a differential signal in a wanted signal pass frequency band and into a common mode signal in an unwanted signal frequency band; and a common mode rejector functioning as a load having an arbitrary impedance with respect to the differential signal outputted from the frequency selective single to differential converter and functioning as a filter with respect to the common mode signal.

Abstract: In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs subsampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain.

Abstract: A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.

Abstract: The present invention provides a signal input device of a digital-RF converter including: a phase-modulated signal input unit configured to input a phase-modulated carrier signal to an LO switch of a digital-RF converter; and a digital signal input unit configured to correct a digital signal to correspond to the phase-modulated carrier signal, and input the corrected digital signal to a data switch of the digital-RF converter.

Abstract: Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.

Abstract: The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.

Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Abstract: There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.

Abstract: Provided is a frequency selective noise canceller including: a frequency selective single to differential converter having a band pass filter function, converting a received single input signal into a differential signal in a wanted signal pass frequency band and into a common mode signal in an unwanted signal frequency band; and a common mode rejector functioning as a load having an arbitrary impedance with respect to the differential signal outputted from the frequency selective single to differential converter and functioning as a filter with respect to the common mode signal.

Abstract: Provided is a digital receiver for use in a wireless communication transmitting/receiving system. The digital receiver oversamples a desired-band signal during performing a subsampling operation for converting an RF signal into an IF signal or DC signal so that an unwanted signal is also converted into a digital signal, and then, eliminated in a digital block.

Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Abstract: There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.

Abstract: A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.

Abstract: An automatic gain-control method for a communication system is comprised of determining a communication distance between the first and second transceivers and controlling gain values of transception stages of the first and second transceivers in correspondence with the communication distance.