Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.

Abstract: A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.

Abstract: A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

Abstract: A variable resistance memory device includes a first electrode layer, a variable resistance layer disposed on the first electrode layer, a second electrode layer disposed on the variable resistance layer, a barrier layer disposed between the variable resistance layer and one of the first and second electrode layers, and a buffer layer disposed between the barrier layer and one of the first and second electrode layers.

Abstract: A semiconductor diode includes a first semiconductor pattern including a first impurity, a first diffusion barrier pattern on the first semiconductor pattern, an intrinsic semiconductor pattern on the first diffusion barrier pattern, a second diffusion barrier pattern on the intrinsic semiconductor pattern, and a second semiconductor pattern including a second impurity on the second diffusion barrier pattern.

Abstract: A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines over the first conductive lines, which extend in a second direction not parallel to the first direction, memory cells including a variable resistance element, each of which is formed at an intersection of the first and second conductive lines, first insulation layer patterns extending in the first direction between the memory cells, second insulation layer patterns extending in the second direction between the memory cells, first thermal barrier layer patterns extending in the first direction, which is spaced apart from the memory cells in the second direction between the first insulation layer patterns, and second thermal barrier layer patterns extending in the second direction, which is spaced apart from the memory cells in the first direction between the second insulation layer patterns.

Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.

Abstract: Provided is an electrical system including an intelligent learning terminal to analyze biometric information associated with a user and calculate an intensity of electrical stimulation for the user based on a result of the analyzing, and at least one wireless electrical stimulator to provide electrical stimulation to the user based on the calculated intensity of electrical stimulation, wherein the intelligent learning terminal is connected to the at least one wireless electrical stimulator based on wired or wireless communication.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

Abstract: The present invention relates to an anti-inflammatory use of macrolactin compounds such as macrolactin A, 7-O-malonyl macrolactin A and 7-O-succinyl macrolactin A, which are produced from a novel Bacillus strain of Bacillus polyfermenticus KJS-2 (KCCM10769P). The macrolactin compounds provided by the present invention were confirmed to greatly suppress the expression and formation of inducible nitric oxide synthetase (iNOS) and cyclooxygenase-2 (COX-2) which are proteins related to the formation of inflammatory mediators, and to accordingly inhibit the formation of nitric oxide (NO) and of prostaglandin E2 (PGE2) which are the metabolites of the proteins. In addition, the macrolactin compounds provided by the present invention were confirmed to have excellent effects in inhibiting the formation of tumor necrosis factor-alpha (TNF-?), interleukin-1? (IL-1?), interleukin-6 (IL-6) and granulocyte macrophage colony-stimulating factor (GM-CSF), which are pro-inflammatory cytokines.

Abstract: An apparatus for saving power in an access point network is provided. The apparatus includes a communication unit that transmits/receives data to/from an access point device through a wireless short distance communication scheme; an input unit that receives a user input; and a controller that controls to determine whether there is a user input through the input unit, generates a deactivation request message including information related to service non-use of the access point device when the user input is not detected for a preset time or longer, and transmits the deactivation request message to the access point device through the communication unit.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.

Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.

Abstract: The present invention relates to an anti-angiogenic composition containing macrolactin compounds such as macrolactin A, 7-O-malonyl macrolactin A, and 7-O-succinyl macrolactin A as active ingredients. The macrolactin compounds according to the present invention strongly suppress angiogenesis in in vivo experiments and can be used as a pharmaceutical composition for preventing or treating diseases caused by angiogenesis.

Abstract: Provided is an electrical system including an intelligent learning terminal to analyze biometric information associated with a user and calculate an intensity of electrical stimulation for the user based on a result of the analyzing, and at least one wireless electrical stimulator to provide electrical stimulation to the user based on the calculated intensity of electrical stimulation, wherein the intelligent learning terminal is connected to the at least one wireless electrical stimulator based on wired or wireless communication.