Patents by Inventor Seong Heo

Seong Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9142635
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Patent number: 9136336
    Abstract: Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Hyun-jong Chung, Hyun-jae Song, Hee-jun Yang, David Seo
  • Patent number: 9108848
    Abstract: Example embodiments relate to methods of manufacturing and transferring a larger-sized graphene layer. A method of transferring a larger-sized graphene layer may include forming a graphene layer, a protection layer, and an adhesive layer on a substrate and removing the substrate. The graphene layer may be disposed on a transferring substrate by sliding the graphene layer onto the transferring substrate.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 18, 2015
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation For Corporate Collaboration
    Inventors: Yun-sung Woo, David Seo, Su-kang Bae, Sun-ae Seo, Hyun-jong Chung, Sae-ra Kang, Jin-seong Heo, Myung-hee Jung
  • Publication number: 20150228804
    Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.
    Type: Application
    Filed: April 22, 2015
    Publication date: August 13, 2015
    Applicant: Seoul National University R&DB Foundation
    Inventors: Jae-ho LEE, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Hyung-cheol SHIN, Jae-hong LEE, Hyun-jong CHUNG, Jin-seong HEO
  • Patent number: 9105556
    Abstract: According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Jae-ho Lee, Hyun-jong Chung
  • Patent number: 9093509
    Abstract: A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seong Heo, Sun-ae Seo, Sung-hoon Lee, Hyun-jong Chung, Hee-jun Yang
  • Patent number: 9064777
    Abstract: According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Seong Heo, Hyun-jong Chung, Hyun-jae Song, Seong-jun Park, David Seo, Hee-jun Yang
  • Patent number: 9053932
    Abstract: A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: June 9, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Wook Lee, Hyeon-jin Shin, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Yun-sung Woo, Jae-ho Lee, Hyun-jong Chung, Jin-seong Heo
  • Publication number: 20150155287
    Abstract: Disclosed are memory devices including a two-dimensional (2D) material, methods of manufacturing the same, and methods of operating the same. A memory device may include a transistor, which includes graphene and 2D semiconductor contacting the graphene, and a capacitor connected to the transistor. The memory device may include a first electrode, a first insulation layer, a second electrode, a semiconductor layer, a third electrode, a second insulation layer, and a fourth electrode which are sequentially arranged. The second electrode may include the graphene, and the semiconductor layer may include the 2D semiconductor. Alternatively, the memory device may include first and second electrode elements, a graphene layer between the first and second electrode elements, a 2D semiconductor layer between the graphene layer and the first electrode element, and a dielectric layer between the graphene layer and the second electrode.
    Type: Application
    Filed: April 30, 2014
    Publication date: June 4, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong HEO, Seong-jun PARK, Hyeon-jin SHIN, Jae-ho LEE
  • Patent number: 9048310
    Abstract: According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: June 2, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R & DB FOUNDATION
    Inventors: Jae-ho Lee, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hyung-cheol Shin, Jae-hong Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 9040957
    Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: May 26, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae-ho Lee, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hyung-cheol Shin, Jae-hong Lee, Hyun-jong Chung, Jin-seong Heo
  • Publication number: 20150137075
    Abstract: Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first transistor and a second transistor that are connected to each other, and the first and second transistor layers may include 2D materials. The first transistor may include a first graphene layer and a first 2D semiconductor layer contacting the first graphene layer, and the second transistor may include a second graphene layer and a second 2D semiconductor layer contacting the second graphene layer. The first 2D semiconductor layer may be a p-type semiconductor, and the second 2D semiconductor layer may be an n-type semiconductor. The first 2D semiconductor layer may be arranged at a lateral side of the second 2D semiconductor layer.
    Type: Application
    Filed: April 30, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seong HEO, Seong-jun PARK, Hyeon-jin SHIN
  • Patent number: 8999201
    Abstract: Graphene, a method of fabricating the same, and a transistor having the graphene are provided, the graphene includes a structure of carbon (C) atoms partially substituted with boron (B) atoms and nitrogen (N) atoms. The graphene has a band gap. The graphene substituted with boron and nitrogen may be used as a channel of a field effect transistor. The graphene may be formed by performing chemical vapor deposition (CVD) method using borazine or ammonia borane as a boron nitride (B-N) precursor.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hoon Lee, Sun-ae Seo, Yun-sung Woo, Hyun-jong Chung, Jin-seong Heo
  • Publication number: 20150056758
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Application
    Filed: October 6, 2014
    Publication date: February 26, 2015
    Inventors: Jin-seong HEO, Hyun-jong CHUNG, Sun-ae SEO, Sung-hoon LEE, Hee-jun YANG
  • Patent number: 8912530
    Abstract: According to example embodiments, an electrode structure includes a graphene layer on a semiconductor layer and an electrode containing metal on the graphene layer. A field effect transistor (FET) may include the electrode structure.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-jun Yang, Seong-jun Park, Hyun-jong Chung, Jin-seong Heo
  • Publication number: 20140335587
    Abstract: There are provided a radiofrequency device for increasing amount of a bioactive substance in a plant cell and a plant cell culture method for increasing amount of useful intracellular secondary metabolites by using the radiofrequency device. The cell culture method of the present invention makes it possible to increase specific secondary metabolites such as daidzein, equol, and the like in a cell and thus can be used for development into various medicines, agricultural pesticides, spices, pigments, food additives, and cosmetics containing bioactive substances. Further, the cell culture method of the present invention improves conventional cell culture methods limitedly used for specific cells or specific metabolites for increasing amount of intracellular bioactive substances and thus can be widely applied to production of cells and secondary metabolites.
    Type: Application
    Filed: November 8, 2013
    Publication date: November 13, 2014
    Applicant: BIO-FD&C Co., LTD
    Inventors: Sang-Hyun MOH, Jeong-Hun LEE, Hyo-Hyun SEO, Dong-Sun SHIN, Moon-Jin CHO, Hyo-Seok KANG, Hae-Soo JUNG, Hyun-Jin OH, Yeong-Wook YU, Ji-Hong MOH, Mun-Seong HEO, Ser-Jong YOO, Hyun-E LEE, Jin-Hyeong LEE, Yu-Ri LEE, Eun-Ae KIM, Seung-Jun LEE
  • Patent number: 8884345
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Publication number: 20140299944
    Abstract: A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the first electrode, the graphene layer, and the semiconductor substrate.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 9, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jong CHUNG, David SEO, Seong-jun PARK, Kyung-eun BYUN, Hyun-jae SONG, Hee-jun YANG, Jin-seong HEO
  • Patent number: 8835899
    Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-jun Yang, Sun-ae Seo, Sung-hoon Lee, Hyun-jong Chung, Jin-seong Heo
  • Publication number: 20140231820
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 21, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho LEE, Hyun-jong CHUNG, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Jin-seong HEO