Abstract: A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.

Abstract: According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm?3, and a depletion width of less than or equal to 3 nm.

Abstract: A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film.

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract: Graphene, a method of fabricating the same, and a transistor having the graphene are provided, the graphene includes a structure of carbon (C) atoms partially substituted with boron (B) atoms and nitrogen (N) atoms. The graphene has a band gap. The graphene substituted with boron and nitrogen may be used as a channel of a field effect transistor. The graphene may be formed by performing chemical vapor deposition (CVD) method using borazine or ammonia borane as a boron nitride (B-N) precursor.

Abstract: According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode.

Abstract: According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.

Abstract: A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Abstract: Graphene, a method of fabricating the same, and a transistor having the graphene are provided, the graphene includes a structure of carbon (C) atoms partially substituted with boron (B) atoms and nitrogen (N) atoms. The graphene has a band gap. The graphene substituted with boron and nitrogen may be used as a channel of a field effect transistor. The graphene may be formed by performing chemical vapor deposition (CVD) method using borazine or ammonia borane as a boron nitride (B—N) precursor.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: A magnetic memory device includes a track in which different non-magnetic layers are respectively formed on upper and lower surfaces of a magnetic layer. One of the two non-magnetic layers includes an element having an atomic number greater than or equal to 12. Accordingly, the magnetic layer has a relatively high non-adiabaticity (?).

Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.

Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.

Abstract: According to example embodiments, a solar cell includes a photovoltaic layer, a plurality of front electrodes, a rear electrode, and a transparent subsidiary electrode. The plurality of front electrodes and the rear electrode are disposed respectively on front and rear surfaces of the photovoltaic layer. The subsidiary electrode is disposed on front surfaces of the photovoltaic layer and the front electrodes. The subsidiary electrode may be graphene.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: Provided is an apparatus for controlling an inverter current, and more particularly, to a current controlling apparatus for controlling current of a switching element of an inverter that outputs a 3-phase alternating current. The apparatus for controlling an inverter current includes: an inverter comprising a plurality of current detection switching elements capable of detecting switched and output current, converting a direct current voltage into a 3-phase alternating current by turning the plurality of current detection switching elements on and off; an AD converter for directly receiving an input of an output current of an output terminal of each of the plurality of current detection switching elements as a detection current and converting the detection current into a detection signal value in digital form; and a control unit for controlling on and off of the plurality of current detection switching elements by using the detection signal value.

Abstract: An information storage device includes a magnetic track and a magnetic domain wall moving unit. The magnetic track has a plurality of magnetic domains and a magnetic domain wall between each pair of adjacent magnetic domains. The magnetic domain wall moving unit is configured to move at least the magnetic domain wall. The information storage device further includes a magneto-resistive device configured to read information recorded on the magnetic track. The magneto-resistive device includes a pinned layer, a free layer and a separation layer arranged there between. The pinned layer has a fixed magnetization direction. The free layer is disposed between the pinned layer and the magnetic track, and has a magnetization easy axis, which is non-parallel to the magnetization direction of the pinned layer.