Patents by Inventor Seong-Il Kim
Seong-Il Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9780176Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.Type: GrantFiled: August 16, 2016Date of Patent: October 3, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong Min Lee, Byoung-Gue Min, Hyung Sup Yoon, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Ho Kyun Ahn, Sang-Heung Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
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Publication number: 20170236909Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.Type: ApplicationFiled: August 26, 2016Publication date: August 17, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho Kyun AHN, Dong Min KANG, Yong-Hwan KWON, Dong-Young KIM, SEONG IL KIM, Hae Cheon KIM, Eun Soo NAM, Jae Won DO, Byoung-Gue MIN, Hyung Sup YOON, Sang-Heung LEE, Jong Min LEE, Jong-Won LIM, Hyun Wook JUNG, Kyu Jun CHO
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Publication number: 20170237171Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the mType: ApplicationFiled: August 5, 2016Publication date: August 17, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong-Young KIM, Dong Min KANG, SEONG-IL KIM, Hae Cheon KIM, Jae Won DO, Byoung-Gue MIN, Ho Kyun AHN, Hyung Sup YOON, Sang-Heung LEE, Jong Min LEE, Jong-Won LIM, Yoo Jin JANG, Hyun Wook JUNG, Kyu Jun CHO, Chull Won JU
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Publication number: 20170133471Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.Type: ApplicationFiled: August 16, 2016Publication date: May 11, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong Min LEE, Byoung-Gue MIN, Hyung Sup YOON, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Hae Cheon KIM, Jae Won DO, Ho Kyun AHN, Sang-Heung LEE, Jong-Won LIM, Hyun Wook JUNG, Kyu Jun CHO, Chull Won JU
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Patent number: 9634112Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: GrantFiled: February 27, 2015Date of Patent: April 25, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup Yoon, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Seong-Il Kim, Sang Heung Lee, Dong Min Kang, Chull Won Ju, Jae Kyoung Mun
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Patent number: 9537458Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.Type: GrantFiled: March 23, 2015Date of Patent: January 3, 2017Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Heung Lee, Dong Min Kang, Seong Il Kim, Ho Kyun Ahn, Hyung Sup Yoon, Jong Won Lim, Chull Won Ju
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Patent number: 9438199Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.Type: GrantFiled: September 5, 2014Date of Patent: September 6, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong Min Kang, Seong Il Kim, Sang Heung Lee, Chull Won Ju, Ho Kyun Ahn, Hyung Sup Yoon, Jong Won Lim
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Publication number: 20160187760Abstract: A liquid crystal lens film structure can includes a first substrate; a second substrate opposite to the first substrate; an adhesive layer on the second substrate; and a liquid crystal lens film between the first substrate and the adhesive layer. The liquid crystal lens film includes a resin layer configured to include a plurality of concave portions and a plurality of liquid crystal portions configured to each include liquid crystal molecules filled in the respective concave portion. The adhesive layer comes in contact with the liquid crystal lens film.Type: ApplicationFiled: December 28, 2015Publication date: June 30, 2016Applicant: LG DISPLAY CO., LTD.Inventors: Seong-il Kim, Su Seok Choi, Jong Hoon Woo, Joong Ha Lee, Sang Hoon Oh
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Publication number: 20160020147Abstract: A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric.Type: ApplicationFiled: September 22, 2015Publication date: January 21, 2016Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jongmin LEE, Byoung-Gue MIN, Seong-il KIM, Hyung Sup YOON, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20150380482Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.Type: ApplicationFiled: March 13, 2015Publication date: December 31, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ho Kyun AHN, Hae Cheon KIM, Jong Won LIM, Dong Min KANG, Yong Hwan KWON, SEONG IL KIM, Zin Sig KIM, Eun Soo NAM, Byoung Gue MIN, Hyung Sup YOON, Kyung Ho LEE, Jong Min LEE, Kyu Jun CHO
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Patent number: 9224830Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.Type: GrantFiled: June 11, 2013Date of Patent: December 29, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong-Il Kim, Jong-Won Lim, Dong Min Kang, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Byoung-Gue Min, Jongmin Lee, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9209266Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.Type: GrantFiled: November 26, 2014Date of Patent: December 8, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Won Lim, Ho Kyun Ahn, Young Rak Park, Dong Min Kang, Woo Jin Chang, Seong-il Kim, Sung Bum Bae, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20150349736Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.Type: ApplicationFiled: March 23, 2015Publication date: December 3, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Heung LEE, Dong Min KANG, SEONG IL KIM, Ho Kyun AHN, Hyung Sup YOON, Jong Won LIM, Chull Won JU
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Patent number: 9178474Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.Type: GrantFiled: July 25, 2013Date of Patent: November 3, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang-Heung Lee, Seong-il Kim, Dong Min Kang, Jong-Won Lim, Chull Won Ju, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
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Patent number: 9166011Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.Type: GrantFiled: July 10, 2014Date of Patent: October 20, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seong Il Kim, Dong Min Kang, Sang Heung Lee, Ho Kyun Ahn, Hyung Sup Yoon, Byoung Gue Min, Jong Won Lim
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Publication number: 20150270822Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.Type: ApplicationFiled: September 5, 2014Publication date: September 24, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Dong Min KANG, Seong Il KIM, Sang Heung LEE, Chull Won JU, Ho Kyun AHN, Hyung Sup YOON, Jong Won LIM
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Publication number: 20150236108Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.Type: ApplicationFiled: July 10, 2014Publication date: August 20, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Seong Il KIM, Dong Min KANG, Sang Heung LEE, Ho Kyun AHN, Hyung Sup YOON, Byoung Gue MIN, Jong Won LIM
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Patent number: 9111506Abstract: A display device includes a plurality of pixels arranged in matrix, a plurality of gate lines, a plurality of data lines, and a gate driver connected to the plurality of gate lines. The gate driver receives a first scan start signal, a second scan start signal and clock signals and outputs a gate-on voltage to each of the plurality of gate lines. The gate driver outputs the gate-on voltage to the plurality of gate lines such that the gate-on voltages do not overlap with each other when the gate driver receives the first scan start signal. The gate driver outputs the gate-on voltage to at least two of the gate lines at substantially the same time when the gate driver receives the second scan start signal.Type: GrantFiled: August 12, 2011Date of Patent: August 18, 2015Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Myung-Ho Won, Min-Sik Um, Seong-Il Kim, Sang-Won Lee, Tae-Seok Ha, Hyo-Sun Kim
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Publication number: 20150194494Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.Type: ApplicationFiled: April 2, 2014Publication date: July 9, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Ho Kyun AHN, Hae Cheon KIM, Zin Sig KIM, Sang Heung LEE, Byoung Gue MIN, Hyung Sup YOON, Dong Min KANG, Seong Il KIM, Jong Min LEE, Jong Won LIM, Yong Hwan KWON, Eun Soo NAM
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Publication number: 20150171188Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue MIN, Jong-Won LIM, Hokyun AHN, Seong-Il Kim, Sang Heung LEE, Dong Min KANG, Chull Won JU, Jae Kyoung MUN