Abstract: A page buffer of a nonvolatile memory device according to the present disclosure comprises a first data latch unit configured to store data for program or program inhibition, a second data latch unit configured to store data for setting threshold voltage states of cells to be programmed, and a 1-bit pass determination unit configured to determine whether a cell to be programmed has been programmed to exceed a verification voltage by grounding or making floating a first verification signal output terminal in response to data set to a first node of the first data latch unit and data applied to a sense node.

Abstract: A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

Abstract: The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.

Abstract: A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of performing program and verification operations, a first data setting step of, when a program pulse is supplied more than N times (where N is a natural number), inputting data for performing a program operation to the first latch of the page buffer to which the memory cells to be programmed with the second threshold voltage distribution are coupled, and a second program and verification step of performing program and verification operations.

Abstract: A method of operating a nonvolatile memory device, including a memory cell array, which further includes a drain select transistor, a memory cell string, and a source select transistor coupled between a bit line and a source line, where the method includes precharging the bit line, setting the memory cell string in a ground voltage state, coupling the memory cell string and the bit line together and supplying a read voltage or a verification voltage to a selected memory cell of the memory cell string, and coupling the memory cell string and the source line together in order to change a voltage level of the bit line in response to a threshold voltage of the selected memory cell.

Abstract: A nonvolatile memory device comprises a page buffer unit, a counter, a program pulse application number storage unit, and a program start voltage setting unit. The page buffer is configured to output a 1-bit pass signal when a cell programmed to exceed a reference voltage, from among target program cells included in a single page, exists. The counter is configured to count a number of program pulses applied to determine a program pulse application number. The program pulse application number storage unit is configured to store a number of program pulses applied until the 1-bit pass signal is received during a program operation for a first page. The program start voltage setting unit is configured to set a program start voltage for a second page based on the stored program pulse application number.

Abstract: A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells.

Abstract: A method of operating a semiconductor memory device according to an aspect of the present disclosure includes performing a program loop, including a program operation and a program verification operation, in order to store input data in selected memory cells, performing a first error bit check operation for comparing the number of error bits of data not identical with the input data, with the number of correctable error bits, if the number of error bits is equal to or smaller than the number of correctable error bits, performing a second error bit check operation for comparing the number of error bits with the reference number of bits for replacement determination, and if the number of error bits is greater than the reference number of bits for replacement determination, updating failed column address information by adding the column address of a memory cell, having the error bits, to the failed column address information.

Abstract: A flash memory device includes a memory cell string including a plurality of memory cells serially coupled to one another between a bit line and a source line, a page buffer configured to perform a precharging operation and a sensing operation with respect to the bit line, and a power supply unit configured to supply a certain supply voltage through the source line before the precharging operation.

Abstract: A method of operating a semiconductor memory device includes performing an LSB program operation for selected memory cells while raising a program voltage, when the threshold voltages of some of the selected memory cells reach a target level, storing data, corresponding to a relevant program voltage, in a first flag cell, performing the LSB program operation for some of the selected memory cells, having threshold voltages not reached the target level, until the threshold voltages of all the selected memory cells reach the target level, and after the LSB program operation is completed, performing an MSB program operation for the selected memory cells by using a program voltage, set based on the data stored in the first flag cell, as a start program voltage.

Abstract: A semiconductor memory device, including a temperature detector configured to output a temperature detection signal in response to a temperature detected in a core region which includes a plurality of memory cells, and a programming voltage generator configured to generate a programming voltage in response to the temperature detection signal and output a generated programming voltage to the core region.

Abstract: A program method of nonvolatile memory devices, which can solve an under program problem by preventing a drop of a verify voltage in the program, and verify operations. According to an aspect of the method, a program operation is performed on a selected memory cell block. Electric charges charged to a channel of memory cell strings included in unselected memory cell blocks are discharged. A verify operation is performed on the selected memory cell block.

Abstract: A method of programming a semiconductor memory device by applying a program voltage to a selected word line in an incremental step pulse program mode includes raising a voltage of precharging a bit line for program inhibition according to an increase in the program voltage applied to the selected word line.

Abstract: A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation.

Abstract: A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a photosensitive metal-organic material precursor solution on a substrate; pressurizing the photosensitive metal-organic material precursor coating layer to a mold patterned to have a protrusion and depression structure; forming the metal oxide thin film pattern by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer to cure it; and removing the patterned mold from the metal oxide thin film pattern.

Abstract: A method of operating a nonvolatile memory device includes performing a first program operation and a first verification operation on memory cells until a cell, having a threshold voltage higher than a first reference voltage, occurs and, when a cell having the threshold voltage higher than the first reference voltage occurs, performing a second program operation and performing a second verification operation using a second reference voltage higher than the first reference voltage.

Abstract: A method of verifying a non-volatile memory device to increase the read margin even though a negative verifying voltage is not applied is disclosed. The method of verifying a non-volatile memory device includes coupling a cell string to a bit line precharged to a high level through a sensing node, the cell string being provided between a common source line and the bit line; applying a verifying voltage to a plurality of word lines associated with the cell string; disconnecting the bit line from the sensing node; coupling the common source line to the cell string while the verifying voltage is applied to the word lines, wherein the common source line is applied with a bias voltage higher than a ground voltage; and coupling the bit line to the sensing node so as to detect a level of the bit line.

Abstract: A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation.

Abstract: A method for forming a metal oxide thin film pattern using nanoimprinting according to one embodiment of the present invention includes: coating a photosensitive metal-organic material precursor solution on a substrate; pressurizing the photosensitive metal-organic material precursor coating layer to a mold patterned to have a protrusion and depression structure; forming the metal oxide thin film pattern by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer to cure it; and removing the patterned mold from the metal oxide thin film pattern.

Abstract: A word line voltage generator that generates a word line voltage, which is selectively changed depending on a temperature, a flash memory device including the word line voltage generator, and a method of generating the word line voltage. The word line voltage generator includes a read voltage generator and a controller. The read voltage generator generates a read voltage or a verify voltage based on one of reference voltages in response to an enable control signal and supplies the read voltage or the verify voltage to one of a plurality of global word lines in response to a row decoding signal, during a read operation or a read operation for program verification, of the flash memory device. The controller generates one of the reference voltages in response to a read control signal or a verify control signal. When a temperature is varied, the read voltage generator changes the level of the read voltage or the verify voltage in reverse proportion to the temperature.