Abstract: A voltage generating circuit and method thereof for preventing a current from flowing from a voltage generating node to a pumping node in transiting of the circuit from an active operation to a pre-charge operation are provided. The voltage generating circuit comprises a pre-charge circuit for pre-charging a pumping node and a voltage transmitting control node during a pre-charge operation; a voltage pumping circuit for pumping a signal at the pumping node during an active operation; a voltage transmitting circuit for transmitting the signal from the pumping node to a voltage generating node in response to a signal at the voltage transmitting control node during the active operation; and a countercurrent preventing circuit for varying the signal at the voltage transmitting control node based on the signal at the pumping node during the pre-charge operation and for preventing a current from flowing between the pumping node and the voltage transmitting control node during the active operation.

Abstract: A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

Abstract: A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

Abstract: A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

Abstract: Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

Abstract: A memory system includes first and second memory devices having commonly connected data terminals and commonly connected memory control signal terminals, e.g., devices in respective first and second independently selectable memory banks that share common data lines and common memory control signal lines, such as column address strobe, row address strobe, write enable, and address signal lines. The first and second memory devices includes respective selective on-die termination (ODT) circuits configured to selectively provide first and second termination impedances at their respective data terminals responsive to a memory control signal at the commonly connected memory control signal terminals. The selective ODT circuits may produce the first termination impedance responsive to a memory write operation, and may produce the second termination impedance responsive to a memory read operation and/or expiration of a predetermined time interval following termination of the memory write operation.

Abstract: Methods of terminating an external transmission line in a memory device having an on-die termination circuit include electrically coupling the termination circuit to the transmission line in response to a control signal which indicates that the memory device is in an active mode or a write mode. The termination circuit has an impedance value that is mismatched with an impedance value of the transmission line. The termination circuit can include an input/output pad, a resistor, and a transistor connected in series to a reference voltage. Also, the termination circuit may be electrically coupled to the transmission line by activating the transistor in the termination circuit to connect the transmission line to the reference voltage in response to the control signal. Related devices are also disclosed.

Abstract: Provided are an on-chip termination apparatus in a semiconductor integrated circuit, and a method for controlling the same. The on-chip termination apparatus is installed in a semiconductor integrated circuit that has an output driver for outputting data to the outside via a pad and a data input circuit for receiving data from the outside via the pad. The on-chip termination apparatus includes an on-chip terminator including at least one terminal resistor electrically connected to the pad; and a terminator control circuit for turning on or off the on-chip terminator in response to an output enable signal that enables or disables the data output circuit, wherein the terminator control circuit turns off the on-chip terminator in the event that the data output circuit is enabled. Therefore, the on-chip termination apparatus is controlled by an output enable signal, thereby reducing timing loss, thus enabling a system to operate at high speed.

Abstract: An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M base-A-level input signals from the M first terminals, respectively, encodes each of AM values represented by the M base-A-level input signals as a different base-K value represented by N base-K-level output signals, A and K are positive integers, and where K>A>1. The converter then outputs the N base-K-level output signals to the N second terminals, respectively.

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract: A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits, The ASMD circuit may include a comparator with first and second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within first and second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within first and second cycles of the input clock.

Abstract: A semiconductor device includes an on-chip termination circuit, a reference voltage generator, and an input buffer. The on-chip termination circuit generates a variable resistance to an input signal based on at least one code signal. The reference voltage generator generates a reference voltage based on the code signal. The input buffer generates an internal signal based on the input signal from the on-chip terminal circuit and based on the reference voltage.

Abstract: Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the inverted version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract: A system and method allows for multiple modes of termination, including termination by a fixed value that is preprogrammed, and by a variable value that can, for example, be measured and determined by a self-calibration circuit. Multiple termination values can be achieved within a single device. This configuration is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.

Abstract: The present invention discloses a circuit and a method for generating an internal clock signal, where the internal clock signal generation circuit includes a first delay portion for delaying an external clock signal by a first delay time, divides for dividing an output signal from the first delay portion, a first signal generator for generating a first signal with a pulse width equivalent to a skew monitor time by delaying an output signal from the divider by a second delay time and by combining the output signal from the divider with a signal delayed by the second delay time, a second signal generater for generating a second signal with a pulse width equivalent to a third delay time at a falling or rising edge of the output signal from the first delay portion, a time/digital signal converter for converting the skew monitor time equavalent to the pulse width of the first signal into first and second digital signals in response to the first signal, and a digital signal/time converter for reproducing the skew m

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the inverted version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract: A memory device and process for improving the state of one or more terminations according to process, voltage, and/or temperature variations, including a delay looped circuit (DLL). The memory device has one or more terminations to which one or more variable resistance circuits are connected and through which one or more external signals are passed for operating the memory device, and a control circuit for generating a control signal for controlling one or more resistance values of the variable resistance circuits, in response to a command enable signal that represents the activation of another operation and an external enable signal that activates the DLL in the memory device. After the state of the one or more terminations is improved by the control signal, the DLL is enabled. External signals can be received after improving the state of the terminations according to process, voltage, and/or temperature variations, thereby improving input/output characteristics.

Abstract: The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging (“post repair”) using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free.

Abstract: A voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat.