Abstract: A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract: An input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof are provided. The example semiconductor memory device may include a clock buffer configured to generate an internal clock signal based on an external clock signal, a command decoder configured to decode an external command signal to generate a write command signal and an input latency control circuit configured to gate an address signal in a pipeline mode to generate a column address signal and a bank address signal based on the internal clock signal, the write command signal and the write latency signal.

Abstract: A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

Abstract: A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver.

Abstract: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

Abstract: A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

Abstract: A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the, read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.

Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information.

Abstract: An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M base-A-level input signals from the M first terminals, respectively, encodes each of AM values represented by the M base-A-level input signals as a different base-K value represented by N base-K-level output signals, A and K are positive integers, and where K>A>1. The converter then outputs the N base-K-level output signals to the N second terminals, respectively.

Abstract: We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

Abstract: A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal in synchronization with each other. The memory circuit, which can be an SDRAM memory circuit, receives the data strobe signal and the data load signal and writes data in response to the two synchronous signals. Because the signal are synchronous, parameters introduced by timing variations caused by different signal domains are eliminated. As a result, high-frequency operation of the system is greatly improved.

Abstract: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data path transfers the sense output signal, and latches the sense output signal to output the sense output signal to the first node. The third data path latches a signal of the first node, and transfers the signal of the first node to generate output data. Accordingly, the semiconductor memory device including the output circuit can operate at a relatively higher frequency using a pseudo-pipeline structured circuit, which combines a wave pipeline structure with a full pipeline structure.

Abstract: A method for activating a word line segment of a semiconductor memory selected based on a row address provided to the memory can include activating a first word line segment selected by a row address and a command type and avoiding activating a second word line segment selected by the row address. Related devices are also disclosed.

Abstract: Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device. The number of registers included in data output paths in the high frequency mode is reduced and the number of control signals used for data input/output of the registers is also reduced. Consequently, loads of the data output paths in the high frequency mode are decreased to improve a high frequency operation and reduce the chip area of the output circuit.

Abstract: A swing limiter comprises: a logic circuit including at least one first pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a second node and receive at least one input signal to generate an output signal, respectively; a second pull-up transistor connected between a first power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the second power voltage in response to a first control voltage; a second pull-down transistor connected between the second node and a second power voltage and causing a voltage of the second node to have a voltage level obtained by adding a voltage which is less than an absolute value of a threshold voltage thereof to the second power voltage in response to a second control voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and

Abstract: A line driver circuit for stabilizing a signal that is output through a transmission line, wherein the line driver circuit receives a first signal having a first swing width corresponding to a difference between a first voltage and a second voltage, creates a second signal having a second swing width less than the first swing width, and outputs the second signal through a transmission line. The line driver circuit includes: a pull-up circuit that pulls up the second signal to a high level; a pull-down circuit that is connected to the pull-up circuit and pulls down the second signal to a low level; and an initializing circuit that is connected to a node of the transmission line, outputs a signal having a voltage of the low level or the high level to the node of the transmission line, and initializes the voltage at the node of the transmission line to the low level or the high level.