Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory cells; and a sense amplifier configured to read data from the plurality of memory cells and output the read data. The sense amplifier includes a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A concentration filter for selectively concentrating a sample, a method for manufacturing the concentration filter, and a sample concentration device are disclosed herein. The selective concentration filter of the present invention comprises: a base having pores; and a selective permeable membrane which is coated on the base and which comprises vesicles, wherein the selective permeable membrane concentrates an analyte to be analyzed from a sample and allows at least a portion of the remaining substances, other than the analyte, to be permeated through a pore structure. According to the present invention, an analyte to be analyzed can be easily concentrated through a simplified structure.

Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.

Abstract: A coil component includes a body having a first surface, a second surface opposing the first surface in a first direction, and side surfaces connecting the first surface and the second surface to each other, a support member disposed in the body, a coil disposed on each of one surface of the support member and the other surface of the support member opposing the one surface in the first direction, including first and second lead-out portions respectively extending to a first side surface and a second side surface of the body opposing each other in a second direction, and a first dummy lead-out portion disposed on the other surface of the support member, and connected to the first lead-out portion. W2/W1 satisfies 0.3 or more and 0.8 or less, W1 is a width of the first lead-out portion, W2 is a width of the first dummy lead-out portion.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A tantalum capacitor includes a tantalum body including a tantalum element, a conductive polymer layer disposed on the tantalum element, and a tantalum wire penetrating through at least a portion of each of the tantalum element and the conductive polymer layer in a first direction, a molded unit surrounding the tantalum body and, an anode lead frame exposed to one surface of the molded unit and connected to the tantalum wire, a cathode lead frame spaced apart from the anode lead frame and exposed to the one surface of the molded unit, and a first coating layer disposed in at least a portion of a region between the molded unit and the anode lead frame and a region between the molded unit and the cathode lead frame.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A terminal assembly of a driving motor includes: a support ring surrounding a stator core to which bobbins are coupled, the bobbins being configured to allow stator coils to be wound thereon; a first sub-assembly disposed on the support ring to surround the bobbins; and a second sub-assembly connected to the first sub-assembly, the second sub-assembly including fixing portions inserted into coupling recesses formed in the bobbins. Three-phase bus bars connected to three-phase lead wires of the stator coils are inserted into the first sub-assembly and an N-phase bus bar connected to N-phase lead wires of the stator coils is inserted into the second sub-assembly.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.

Abstract: Proposed are a laminating apparatus and a method for manufacturing a vehicle seat. The laminating apparatus includes a first lamination part (100); a second lamination part (200); and a drying part (300), wherein the first lamination part (100) includes: a polyurethane foam feeding roll (110); a first bonding part (120); a fabric feeding roll (130) mounted on a side of the first lamination part (100); and a first pressing part (140), the second lamination part (200) includes: a second application part (210); a backing cloth feeding roll (220); and a second pressing part (230), and the drying part (300) includes: a feed part (310); and a chamber part (320).

Abstract: A terminal assembly of a driving motor includes: a support ring surrounding a stator core to which bobbins are coupled, the bobbins being configured to allow stator coils to be wound thereon; a first sub-assembly disposed on the support ring to surround the bobbins; and a second sub-assembly connected to the first sub-assembly, the second sub-assembly including fixing portions inserted into coupling recesses formed in the bobbins. Three-phase bus bars connected to three-phase lead wires of the stator coils are inserted into the first sub-assembly and an N-phase bus bar connected to N-phase lead wires of the stator coils is inserted into the second sub-assembly.

Abstract: Provided is a method for treating or preventing cancer, containing, as an active ingredient, a compound having a specific chemical structure and an activity of inhibiting the formation of a c-Myc/Max/DNA complex, or a pharmaceutically acceptable salt thereof.

Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.

Abstract: The present invention relates to a pharmaceutical composition for the prophylaxis or treatment of cancer comprising a novel azolopyrimidine heterocyclic compound as an active ingredient, and the pharmaceutical composition for the prophylaxis or treatment of cancer of the present invention can be used as a small molecular immunotherapy anticancer agent which modulates an adenosine pathway by comprising the azolopyrimidine heterocyclic compound.