Abstract: A shallow trench isolation (STI) structure and method of fabrication includes a two-step epitaxial growth process. A trench larger than the target STI structure is etched into a semiconductor substrate, a first layer of un-doped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth and a critical dimension, and a second layer of doped semiconductor material epitaxially grown on the first layer, said second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate.

Abstract: A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.

Abstract: A fully depleted silicon on insulator (FDSOI) is employed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.) associated with the diffusion regions of a pixel cell. The buried oxide (BOX) layer, for example, fully isolates the transistor channel region, such as an (N) channel region of the pixel cell from the photodiode(s) of the pixel region, eliminating the junction leakage path, thus leading to a reduction in diffusion leakage and an increase device operation speed. An increase of full well capacity can also be realized by the absence of isolation structure, such as trench isolation or isolation implant structure.

Abstract: Image sensors include a photodiode formed in a substrate material and a transistor coupled to the photodiode. The transistor has a trench structure formed in the substrate material, an isolation layer disposed on the substrate material, and a gate disposed on the isolation layer and extending into the trench structure. The trench structure has a polygonal cross section in a channel width plane, the polygonal cross section defining at least four sidewall portions of the substrate material, which contribute to an effective channel width measured in the channel width plane that is wider than a planar channel width of the transistor.

Abstract: An image sensor includes a substrate material. The substrate material includes a plurality of photodiodes disposed therein. The plurality of photodiodes includes a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) larger than the SPDs. An array of color filters is disposed over the substrate material. A buffer layer is disposed between the substrate material and the array of color filters. A metal pattern is disposed between the color filters in the array of color filters, and between the array of color filters and the buffer layer. An attenuation layer is disposed between the substrate material and the array of color filters. The attenuation layer is above and aligned with the plurality of SPDs and a portion of each of the plurality of LPDs. An edge of the attenuation layer is over one of the plurality of LPDs.

Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

Abstract: An image sensor includes a plurality of photodiodes arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive incoming light through a backside of the semiconductor substrate. A front side of the semiconductor substrate is opposite from the backside. A plurality of deep trench isolation (DTI) structures are formed laterally with respect to the photodiodes on the backside of the semiconductor substrate. The plurality of DTI structures are arranged between adjacent photodiodes. A plurality of pillar structures extend from a metal grid proximate to the backside and is formed proximate to the backside and aligned with the DTI structures.

Abstract: An inverter structure includes a p-type field effect transistor (PFET) including a PFET source, a PFET drain and a PFET gate; a n-type field effect transistor (NFET) including an NFET source, an NFET drain and an NFET gate. The NFET is adjacent to the PFET, and the PFET drain and the NFET drain form an output node and the PFET gate and the NFET gate are electrically connected to form an input node. A zero via layer includes: at least one first contact electrically coupled to the PFET source, at least one second contact electrically coupled to the NFET source, and at least one third contact electrically coupled to the output node. Each third contact has a smaller width in a fin-length direction than each first contact and each second contact to improve RC delay and overall performance.

Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract: A wide-bottom contact to epitaxial structures in a non-planar semiconductor structure is provided. A starting structure includes a non-planar semiconductor structure, the structure including a semiconductor substrate, fins coupled to the substrate, and epitaxial structures (e.g., diamond-shaped silicon epitaxy) on the fins. Trenches to the epitaxial structures with roughly vertical sidewalls are created from a field oxide and photoresist. Silicide is formed on the epitaxial structures, and bottom contact portions (of metal, e.g., tungsten) are conformally created on the silicide. The vertical sidewalls allow for a wider bottom. Contact bodies are then formed on the bottom contact portions.

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: loading a wafer into a chamber including a ceramic dome coated with a material having etch tolerance against a plasma; etching a gate structure formed on the wafer, thereby generating etch remnants; and removing the etch remnants by using a gas of SF6 as a main etch gas.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: loading a wafer into a chamber including a ceramic dome coated with a material having etch tolerance against a plasma; etching a gate structure formed on the wafer, thereby generating etch remnants; and removing the etch remnants by using a gas of SF6 as a main etch gas.

Abstract: A system for etching polysilicon in fabricating a semiconductor device is disclosed, which can prevent contamination of a wafer with polymers formed during a polysilicon etching process in which the polysilicon coated on the wafer is selectively etched. The system includes a reaction chamber having a wafer chuck placed therein on which a wafer is loaded for proceeding an etching process, a passage for discharging a reaction gas from the reaction chamber, a vacuum pump disposed below one side of the passage for pumping out the gas inside of the reaction chamber, a pressure control valve disposed at an inlet to the vacuum pump for controlling a flow rate of the gas being pumped, and a valve driving motor for driving the pressure control valve.