Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

Abstract: The liquid crystal display includes a substrate, and pixel electrodes are formed on the substrate, each of which has first and second subpixel electrodes. Each of the first and second subpixel electrodes has at least two parallelogrammic electrode pieces, each of which has lengthwise edges and oblique edges adjacent to the lengthwise edges.

Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

Abstract: A thin film transistor is provided, which includes: a gate electrode (124); a gate insulating layer (140) formed on the gate electrode; a semiconductor layer (154) formed on the gate insulating layer and disposed opposite the gate electrode; a source electrode (173) and a drain electrode (175) that are formed at least in part on the semiconductor layer and face each other, a passivation layer (180) formed on the source electrode, the drain electrode, and a portion of the semiconductor layer that is not covered with the source electrode and the drain electrode; and a shielding electrode (196) formed on the passivation layer and disposed on a region between the source electrode and the drain electrode.

Abstract: A gate driver circuit includes a driving section and a wiring section. The wiring section receives a plurality of signals from an external device. The driving section includes a plurality of stages providing a plurality of gate lines with a gate signal. The wiring section includes first and second signal wirings. The first signal wiring is disposed adjacent to a first side of the driving section, where the first side receives the signals from the wiring section. The second signal wiring is disposed adjacent to a portion that is disposed at an outer side of the driving section and the first signal wiring. Therefore, a signal applied to the first signal wiring is prevented from being delayed by the second signal wiring. Furthermore, a distortion of signal applied to the gate driver and a maloperation of the gate driver are prevented.

Abstract: Disclosed is a thin film transistor array panel. The panel includes a plurality of pixels arranged in the form of a matrix each with a pixel electrode and a switching element connected to the pixel electrode, and a plurality of gate lines connected to the switching elements and extending in the row direction. A pair of the gate lines are connected to pixels in each pixel row. A plurality of data lines are connected to the switching elements, and elongated in the column direction. Each data line is provided between two columns of the pixels. The respective data lines are horizontally bent between the two adjacent gate lines, and vertically extend between the two pixel rows.

Abstract: A display device including a plurality of pixel electrodes arranged in a matrix including rows and columns and a plurality switching elements coupled with the pixel electrodes; a plurality of gate lines coupled with the switching elements and extending in a row direction, at least two gate lines assigned to a row; and a plurality of data lines coupled with the switching elements and extending in a column direction, a data line assigned to at least two columns, wherein each of the pixel electrodes has a first side and a second side that is farther from a data line than the first side, and the switching elements are disposed near the second sides of the pixel electrodes.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

Abstract: In a driving unit (e.g., a gate driving unit) and a flat panel display apparatus having the driving unit, a circuit portion of the driving unit includes a plurality of driving stages cascade-connected to one another and outputs a (gate) driver signal (a plurality of gate-driving signals) based on a plurality of control signals. The line portion comprises a first signal line and a second signal line, each of which transmits control signals from the outside, and a first connection line connecting the first signal line to the driving stages, and a second connection line connecting the second signal line to the driving stages. The second signal line is positioned at a different (metallization) layer from the first signal line and the first and second connection lines. Therefore, malfunctioning of the driving unit caused by corrosion may be prevented.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.

Abstract: In accordance with one or more embodiments of the present invention, a driving portion of a display device is formed on the same plane as a display portion of a display device. The driving portion includes cumulative layers of a control electrode, a first insulating layer, a semiconductor layer, a second insulating layer, an input electrode, an output electrode, and an auxiliary layer on top of the layers. Thus, the transistors within the driving portion may be more compact, while possibly reducing the likelihood of a short circuit between the electrodes.

Abstract: A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.

Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: A gate line is formed on a substrate, and a gate insulating layer is formed thereon. A data line is formed on the gate insulating layer, and a passivation layer is formed on the data line. The passivation layer has an opening exposing the gate insulating layer. A pixel electrode is formed on the passivation layer and it overlaps the data line and the passivation layer.