Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes a pixel electrode having first and second sub-pixel electrodes; a first thin film transistor connected to the first sub-pixel electrode; a second thin film transistor connected to the second sub-pixel electrode; a first data line connected to the first thin film transistor; a second data line connected to the second thin film transistor; a gate line connected to the first and second thin film transistors and crossing the first and second data lines; and a blocking member overlapping at least one portion of the first sub-pixel electrode.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: The liquid crystal display device includes a first insulation substrate, a gate line which is disposed on the first insulation substrate and extends substantially in a first direction, first and second data lines which are insulated from the gate line, extend substantially in a second direction and intersect the gate line, a pixel electrode which includes first and second sub-pixel electrodes which are each provided with different data voltages via the first and second data lines, respectively, and which are separated from each other by a gap, the second sub-pixel electrode at least partially overlapping the first and second data lines, a second insulation substrate which faces the first insulation substrate, a black matrix which is disposed on the second insulation substrate and includes an irregular shape and extends substantially along the first and second data lines and a liquid crystal layer which is interposed between the first and second insulation substrates.

Abstract: A gate drive circuit includes m stages cascade connected to one another, each stage respectively outputting one of a plurality of gate signals. An m-th stage includes a pull-up part, a pull-down part, a boost-up part, a first maintenance part and a second maintenance part. The pull-up part outputs a high voltage of a first clock signal at the high voltage of an m-th gate signal. The pull-down part applies a low voltage to an output node of the pull-up part. The boost-up part boosts a voltage charged by an offset second clock signal. The first maintenance part maintains the first node at a low voltage in response to the boosted voltage of the second node. In addition, the second maintenance part maintains the m-th gate signal at the low voltage in response to the high voltage of the first clock signal.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A liquid crystal display including the first and second substrates facing each other and a liquid crystal layer interposed between the first and second substrates is provided. A storage electrode, a transparent insulating layer pattern, and a pixel electrode are formed on the first substrate. A common electrode having a domain divider is formed on the second substrate. The transparent insulating layer pattern includes an opening having a first area having a first width and a second area having a second width narrower than the first width. The domain divider partially overlaps the storage electrode in the second area of the opening of the transparent insulating layer pattern.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole.

Abstract: A liquid crystal display includes a substrate, a plurality of a gate line and a plurality of a data line disposed on the substrate, a plurality of a thin film transistor each connected to a gate line and a data line, a plurality of a pixel electrode each connected to a thin film transistor, a common electrode facing the pixel electrodes, and a liquid crystal layer between the pixel electrodes and the common electrode. Each of the pixel electrodes includes a first longitudinal edge adjacent to a first data line and a second longitudinal edge adjacent to a second data line adjacent to the first data line. A first distance between an edge of the first longitudinal edge and the first data line is larger than a second distance between the second longitudinal edge and an edge of the second data line.

Abstract: A liquid crystal display (“LCD”) has first, second, and third pixels adjacent to one another in a column direction. The LCD includes a first gate line connected to each of the second and third pixels in common, a capacitance electrode line connected to each of the first and second pixels in common, a first data line connected to the second pixel, and a second data line connected to the first and third pixels.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.

Abstract: A liquid crystal display capable of reducing the stray capacitance of a non-display region and a method of manufacturing the same. The liquid crystal display includes a first substrate, gate lines and data lines intersecting each other on the first substrate to define pixels, a second substrate arranged opposite to the first substrate, a common electrode formed in a display area of the second substrate in which an image is displayed, and a floating electrode formed in a non-display region of the second substrate in which no image is displayed.

Abstract: A gate driver circuit includes a driving section and a wiring section. The wiring section receives a plurality of signals from an external device. The driving section includes a plurality of stages providing a plurality of gate lines with a gate signal. The wiring section includes first and second signal wirings. The first signal wiring is disposed adjacent to a first side of the driving section, where the first side receives the signals from the wiring section. The second signal wiring is disposed adjacent to a portion that is disposed at an outer side of the driving section and the first signal wiring. Therefore, a signal applied to the first signal wiring is prevented from being delayed by the second signal wiring. Furthermore, a distortion of signal applied to the gate driver and a maloperation of the gate driver are prevented.

Abstract: A thin film transistor (“TFT”) array panel includes; a substrate including a display and peripheral area, a display area signal line and a display area TFT disposed in the display area, the display area TFT connected to the display area signal line, a plurality of peripheral area signal lines, a light blocking member disposed on the display area signal line, the display area TFT, and the peripheral area signal lines, a transparent connector connecting one of peripheral area signal lines and another one of the peripheral area signal lines through a contact hole passing through the light blocking member, a pixel electrode connected to the display area TFT, a spacer disposed on a layer above the light blocking member, and a light blocking assistance member composed of the same material as the spacer on the transparent connector, the light blocking assistance member covering at least the contact hole.

Abstract: A liquid crystal display device including a first substrate, a second substrate which faces the first substrate and a liquid crystal layer which is interposed between the first and second substrates. The first substrate comprises an insulating substrate, a gate line which is disposed on the insulating substrate, data wires which comprises first and second data lines insulatedly crossing the gate line. The first substrate includes a first drain electrode electrically connected with the first data line, and a second drain electrode electrically connected with the second data line, a pixel electrode which comprises a first sub-pixel electrode electrically connected with one of the first and second drain electrodes, and a second sub-pixel electrode separated from the first sub-pixel electrode and electrically connected with the other one of the first and second drain electrodes. A semiconductor layer is disposed between the data wires and the insulating substrate.

Abstract: A thin film transistor array panel includes; a substrate including a display area and a peripheral area, a display area signal line disposed in the display area, a display area thin film transistor connected to the display area signal line, a plurality of peripheral area signal lines disposed in the peripheral area, a light-blocking member disposed on the display area signal line, the display area thin film transistor, and the plurality of peripheral area signal lines, a transparent connection electrically connecting the plurality of peripheral area signal lines to each other through a plurality of first contact holes, and a pixel electrode connected to the display area thin film transistor through a second contact hole, wherein an area density of the first contact hole in the peripheral area is less than or equal to about three times an area density of the second contact hole in the display area.

Abstract: A method of manufacturing a display panel includes forming a first display substrate including a plurality of pixel electrodes, a plurality of test signal lines, and a plurality of test pads, forming a second display substrate including a common electrode, forming a short point at a position corresponding to the test pads, dividing the second display substrate into a plurality of regions insulated from each other, aligning and attaching the first display substrate and the second display substrate to each other, removing an edge portion of the first display substrate to expose an edge portion of the second display substrate, and applying a voltage to the first display substrate and the second display substrate through a voltage application portion of the exposed edge portion of the second display substrate.

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.

Abstract: A liquid crystal display includes; a pair of gate lines including a first gate line and a second gate line, a first data line and a second data line which neighbor each other, each of which is disposed substantially perpendicular to the first gate line and the second gate line, a first thin film transistor connected to the first gate line and the first data line, a second thin film transistor connected to the second gate line and the first data line, the second thin film transistor including a drain electrode, and a pixel electrode including a first subpixel electrode electrically connected to the first thin film transistor and a second subpixel electrode electrically connected to the second thin film transistor, wherein the first subpixel electrode is disposed a horizontal distance apart from the first data line and the second data line such that it does not overlap the first data lien and the second data line as seen from a top plan view, and the second subpixel electrode overlaps both the first data line a

Abstract: In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.