Abstract: Apparatus for measuring and/or monitoring a process variable of a medium. The apparatus includes: an oscillatable unit; a driver/receiver unit, which excites the oscillatable unit to oscillate, and/or which receives its oscillations; a control/evaluation unit, which controls the driver/receiver unit, and/or which evaluates the oscillations of the oscillatable unit; and at least one transmitting line and one receiving line between the control/evaluation unit and the driver/receiver unit. At least a third line is provided, which is embodied and arranged in a manner such that it is located between the transmitting line and the receiving line, and is connected with a voltage source, which has an output impedance, which is smaller than the impedance of a condensate bridge.

Abstract: A method and cleaning solution that removes contaminants from a dielectric material and polished surfaces of copper interconnect structures prior to an electroless deposition of a capping layer without substantially adversely affecting the interconnect formed therefrom are disclosed. The cleaning solution includes combinations of a core mixture and sulfuric acid or sulfonic compounds such as sulfonic acids that include methanesulfonic acid. In one embodiment, the core mixture includes a citric acid solution and a pH adjuster such as tetra-methyl ammonium hydroxide or ammonia. One embodiment of the method includes providing a planarized substrate, applying the cleaning solution to the substrate to simultaneously clean at least one metal feature and a dielectric material of the substrate, and depositing the metal capping layer selectively on the at least one metal feature using electroless deposition.

Abstract: A method of fabricating a semiconductor device, having a Cu—Zn alloy thin film (30) formed on a Cu surface (20) by electroplating the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform Cu—Zn alloy thin film (30) for reducing electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving Cu interconnect reliability, and for increasing corrosion resistance.

Abstract: A semiconductor component having a metallization system that includes a multi-metal seed layer and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a lower level interconnect. A hardmask is formed over the dielectric layer and an opening is etched through the hardmask into the dielectric layer. The opening is lined with a thin conformal barrier material. A plurality of metal oxide layers are formed over the conformal barrier material. The plurality of metal oxide layers are reduced by heat treatment to form a multi-metal seed layer. An electrically conductive material is formed over the multi-metal seed layer.

Abstract: The present invention relates to the semiconductor device fabrication industry. More particularly a semiconductor device, having an interim reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35).

Abstract: Embodiments of the present invention relate to an apparatus and method of annealing substrates in a thermal anneal chamber and/or a plasma anneal chamber before electroless deposition thereover. In one embodiment, annealing in a thermal anneal chamber comprises heating the substrate in a vacuum environment while providing a gas, such as a noble gas, a reducing gas such as hydrogen gas, a non-reducing gas such as nitrogen gas, or combinations thereof. In another embodiment, annealing in a plasma chamber comprises annealing the substrate in a plasma, such as a plasma from an argon gas, helium gas, hydrogen gas, or combinations thereof.

Abstract: In one embodiment, a method for depositing a capping layer on a substrate surface containing a copper layer is provided which includes exposing the substrate surface to a zinc solution to form a zinc layer on the copper layer. The method further includes exposing the substrate surface to a silver solution to form a silver layer on the zinc layer, and depositing the capping layer on the silver layer by an electroless deposition process. A second silver layer may be formed on the capping layer, if desired. In another embodiment, a composition of a deposition solution to deposit a cobalt tungsten alloy is disclosed. The deposition solution includes CaWO4, a cobalt source in a range from about 50 mM to about 500 mM, a complexing agent in a range from about 100 mM to about 700 mM and a buffering agent in a range from about 50 mM to about 500 mM.

Abstract: A method for fabricating a capping layer with enhanced barrier resistance to both copper and oxygen diffusion, comprises forming a capping layer on a conductive surface of an interconnect, wherein the capping layer comprises cobalt (Co), tungsten (W), rhenium (Re), and at least one of phosphorus (P) and boron (B). In an embodiment of the invention, forming the capping layer comprises exposing the conductive surface to an electroless capping solution comprising a cobalt source, a tungsten source, a rhenium source, and at least one of a phosphorus source and a boron source, and annealing the capping layer.

Abstract: Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.

Abstract: An apparatus and a method of controlling an electroless deposition process by directing electromagnetic radiation towards the surface of a substrate and detecting the change in intensity of the electromagnetic radiation at one or more wavelengths reflected off features on the surface of the substrate. In one embodiment the detected end of an electroless deposition process step is measured while the substrate is moved relative to the detection mechanism. In another embodiment multiple detection points are used to monitor the state of the deposition process across the surface of the substrate. In one embodiment the detection mechanism is immersed in the electroless deposition fluid on the substrate. In one embodiment a controller is used to monitor, store, and/or control the electroless deposition process by use of stored process values, comparison of data collected at different times, and various calculated time dependent data.

Abstract: Embodiments of the invention generally provide a fluid processing platform. The platform includes a mainframe having a substrate transfer robot, at least one substrate cleaning cell on the mainframe, and at least one processing enclosure. The processing enclosure includes a gas supply positioned in fluid communication with an interior of the processing enclosure, a first fluid processing cell positioned in the enclosure, a first substrate head assembly positioned to support a substrate for processing in the first fluid processing cell, a second fluid processing cell positioned in the enclosure, a second head assembly positioned to support a substrate for processing in the second fluid processing cell, and a substrate shuttle positioned between the first and second fluid processing cells and being configured to transfer substrates between the fluid processing cells and the mainframe robot.

Abstract: An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Abstract: Embodiments of the invention generally provide compositions of activation-alloy solutions, methods to deposit activation-alloys and electronic devices including activation-alloys and capping layers. In one embodiment, a method for depositing a capping layer for a semiconductor device is provided which includes exposing a conductive layer on a substrate surface to an activation-alloy solution, forming an activation-alloy layer on the conductive layer using the activation-alloy solution, and depositing the capping layer on the activation-alloy layer using an electroless deposition solution.

Abstract: A method of fabricating a semiconductor device, having a reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and annealing the electroplated Cu—Zn alloy thin film (30); and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform reduced-oxygen Cu—Zn alloy thin film (30), having a controlled Zn content, for reducing electromigration on the Cu—Zn/Cu structure by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving device reliability, and for increasing corrosion resistance.

Abstract: A method of reducing electromigration in a dual-inlaid copper interconnect line (3) by filling a via (6) with a Cu-rich Cu—Zn alloy (30) electroplated on a Cu surface (200 from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu—Zn alloy as fill (30) for the via (6) in forming the dual-inlaid interconnect structure (35). The alloy fill (30) is formed by electroplating the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill (30) on the Cu surface (20); and annealing the electroplated Cu—Zn alloy fill (30); and planarizing the Cu—Zn alloy fill (30), thereby forming the dual-inlaid copper interconnect line (35).

Abstract: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed.

Abstract: A precursor of a low-k porous dielectric is applied to an integrated circuit substrate. The precursor comprises a host thermosetting material and a porogen. Crosslinking of at least some of the first host thermosetting material is produced to form a low-k dielectric matrix without decomposing all of the porogen. This leaves a solid nonporous layer of the low-k dielectric matrix. Wiring elements are then inlaid in the low-k dielectric matrix. After the wiring elements are formed, remaining porogen is decomposed to leave pores in the low-k dielectric matrix. The resulting wiring elements are smooth walled.

Abstract: A method of fabricating a semiconductor device having copper (Cu) interconnect lines, formed in vias, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution.

Abstract: A method of reducing electromigration in a graded reduced-oxygen dual-inlaid copper interconnect line by filling a via with a graded Cu-rich Cu—Zn alloy fill electroplated on a Cu surface using a stable chemical solution, and by controlling and ordering the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a graded reduced-oxygen Cu—Zn alloy as fill for the via in forming the dual-inlaid interconnect structure. The graded alloy fill is formed by electroplating, while varying electroplating parameters, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the graded fill on the Cu surface; and annealing the electroplated graded Cu—Zn alloy fill; and planarizing the Cu—Zn alloy fill, thereby forming the graded reduced-oxygen dual-inlaid copper interconnect line.