Patents by Inventor Sergey Lopatin

Sergey Lopatin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6624075
    Abstract: A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: September 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Alexander H. Nickel
  • Patent number: 6624074
    Abstract: A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X═C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: September 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Joffre F. Bernard, Paul L. King
  • Patent number: 6621165
    Abstract: A semiconductor device having contaminant-reduced calcium-copper (Ca—Cu) alloy surfaces formed on Cu interconnects fabricated by cost-effectively removing the contaminant layer.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: September 16, 2003
    Inventors: Sergey Lopatin, Paul L. King, Joffre F. Bernard
  • Patent number: 6563222
    Abstract: A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 13, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Takeshi Nogami, Sergey Lopatin
  • Patent number: 6559546
    Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: May 6, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Sergey Lopatin
  • Patent number: 6528424
    Abstract: A method of fabricating a semiconductor device, having a Cu-rich Cu—Zn alloy thin film (30) formed on a cathode-wafer such as a Cu surface (20) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and a semiconductor device thereby formed. The method controls the parameters of pH, temperature, and time in order to form a uniform Cu-rich Cu—Zn alloy thin film (30) for reducing electromigration on the cathode-wafer by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate, for improving device reliability, and for increasing corrosion resistance.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Alexander H. Nickel
  • Patent number: 6528412
    Abstract: For filling an interconnect opening within an insulating layer on a semiconductor wafer, an adhesion skin layer is deposited conformally onto an underlying material comprised of one of a barrier material or a dielectric material at sidewalls and a bottom wall of the interconnect opening. The adhesion skin layer includes a metal alloy doping element. A conformal seed layer is deposited onto the adhesion skin layer using a conformal deposition process, such as an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process. The adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material at the sidewalls and the bottom wall of the interconnect opening. The interconnect opening is filled with a conductive material grown from the conformal seed layer. In this manner, the adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material to minimize electromigration failure of the interconnect.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Sergey Lopatin
  • Patent number: 6528409
    Abstract: For fabricating an interconnect structure within an interconnect opening formed within a porous dielectric material, the interconnect opening is initially formed within a low-K precursor material that is not completely cured. The interconnect opening is then filled with a conductive fill material being contained within the interconnect opening and with a top surface of the conductive fill material within the interconnect opening being exposed. A capping material is formed on the top surface of the conductive fill material, and the capping material is an amorphous alloy or is a microcrystalline alloy having stuffed grain boundaries. A thermal curing process is then performed for curing the low-K precursor material to become a porous low-K dielectric material.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: March 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Fei Wang, Diana Schonauer, Steven C. Avanzino
  • Patent number: 6515368
    Abstract: A method of reducing electromigration in copper interconnect lines by restricting Cu-diffusion pathways along a Cu surface via doping the Cu surface with Zn from an interim copper-zinc alloy (Cu—Zn) thin film electroplated on the copper (Cu) surface from a stable chemical solution, and controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using interim reduced-oxygen Cu—Zn alloy thin films for forming an encapsulated dual-inlaid interconnect structure. The films are formed by electroplating a Cu surface via by electroplating, the Cu surface in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin films and a Cu-fill; and planarizing the interconnect structure.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Alexander H. Nickel
  • Patent number: 6509262
    Abstract: A method of fabricating a semiconductor device having copper (Cu) interconnect lines, formed in vias, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: January 21, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sergey Lopatin
  • Patent number: 6500743
    Abstract: A method for manufacturing a field effect transistor (100) includes forming a gate structure (104) on a surface of a semiconductor substrate and forming first and second spacers (126, 126) on opposing sides of the gate structure. The method further includes etching a top portion of the gate structure and the first and second spacers to define a trench (1502). Subsequently, by a damascene process, at least a portion of the trench is filed with a barrier-high conductivity metal such as copper (1604) to form a T-gate.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 31, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Steven C. Avanzino, Matthew Buynoski
  • Patent number: 6498093
    Abstract: For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: December 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Sergey Lopatin
  • Patent number: 6495443
    Abstract: A method of re-working a semiconductor device having a defective copper damascene interconnect structure, including the steps of obtaining a semiconductor wafer having at least one defect in a copper damascene interconnect structure; placing the wafer in an electrolyte in an electrolytic cell such that the defective copper damascene interconnect structure forms an anode; applying electrical current to the wafer to remove from the wafer substantially all copper from the defective copper damascene interconnect structure; re-applying copper to the semiconductor wafer to form a copper damascene interconnect structure.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: December 17, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Richard J. Huang
  • Patent number: 6486560
    Abstract: A semiconductor device fabricated by a method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution. The method reduces the drift velocity, thereby decreasing the Cu migration rate in addition to void formation rate.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: November 26, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sergey Lopatin
  • Patent number: 6482656
    Abstract: A semiconductor device including a damascene superconducting interconnect, formed of a Ba—Cu—Ca—O superconducting material. A method of forming a superconducting damascene interconnect structure, and the structure made thereby, the method including forming a cavity in an interlevel dielectric; forming a barrier layer in the cavity; forming a seed layer in the cavity over the barrier layer; forming a Cu—Ba alloy layer; filling the cavity by depositing a Cu—Ca—O film; and annealing in oxygen flow to form a Ba—Cu—Ca—O superconductor on the barrier layer. In an alternate embodiment, no barrier layer is formed.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: November 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sergey Lopatin
  • Patent number: 6475272
    Abstract: A nontoxic aqueous chemical solution for forming a Cu—Ca—O thin film on a Cu surface. Specifically, the present invention chemical solution is used to form a thin film which reduces electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to void formation rate.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 5, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sergey Lopatin
  • Patent number: 6472310
    Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: October 29, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Krishnashree Achuthan, Sergey Lopatin
  • Patent number: 6469387
    Abstract: A method of fabricating a semiconductor device having contaminant-reduced Ca-doped Cu surfaces formed on Cu interconnects by cost-effectively depositing a Cu—Ca—X surface and subsequently removing the contaminant layer contained therein; and a device thereby formed. In the Cu—Ca—X surface, where contaminant X=C, S, and O, removal of the contaminant from such surface is achieved by (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Cu—Ca—X surface under vacuum onto the underlying Cu interconnect material to form a Cu—Ca film on Cu interconnect structure, thereby producing a uniform Cu—Ca film (i.e., Cu-rich with 0.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: October 22, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Joffre F. Bernard, Paul L. King
  • Patent number: 6455425
    Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Darrell M. Erb, Sergey Lopatin
  • Patent number: 6447933
    Abstract: An alloy material is formed on an underlying material, and the alloy material comprises an alloy doping element mixed into a bulk material. A first layer of material including the alloy doping element is deposited on the underlying material using a first type of deposition process. The first type of deposition process is corrosion resistive to the underlying material according to one aspect of the present invention. A second layer of material including the bulk material is deposited on the first layer of material using a second type of deposition process. A thermal anneal may be performed by heating the first layer of material and the second layer of material such that the alloy doping element is mixed into the bulk material to form the alloy material on the underlying material. The alloy doping element of the first layer of material deposited on the underlying material promotes adhesion of the alloy material to the underlying material.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pin-Chin C. Wang, Sergey Lopatin