Patents by Inventor Seung-Ha Choi
Seung-Ha Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110297930Abstract: A TFT display panel having a high charge mobility and making it possible to obtain uniform electric characteristics with respect to a large-area display is provided as well as a manufacturing method thereof. A TFT display panel includes a gate electrode formed on an insulation substrate, a first gate insulting layer formed of SiNx on the gate electrode, a second gate insulting layer formed of SiOx on the first gate insulting layer, an oxide semiconductor layer formed to overlap the gate electrode and having a channel part, and a passivation layer formed of SiOx on the oxide semiconductor layer and the gate electrode, and the passivation layer includes a contact hole exposing the drain electrode. The contact hole has a shape in which the passivation layer of a portion directly exposed together with a metal occupies an area smaller than the upper passivation layer.Type: ApplicationFiled: June 1, 2011Publication date: December 8, 2011Inventors: Seung-Ha CHOI, Kyoung-Jae Chung, Woo-Geun Lee
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Publication number: 20110297931Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.Type: ApplicationFiled: August 15, 2011Publication date: December 8, 2011Inventors: Dong-Ju YANG, Yu-Gwang JEONG, Ki-Yeup LEE, Sang-Gab KIM, Yun-Jong YEO, Shin-Il CHOI, Hong-Kee CHIN, Seung-Ha CHOI, Jung-Suk BANG
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Patent number: 8067774Abstract: After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.Type: GrantFiled: May 4, 2009Date of Patent: November 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Ha Choi, Ki-Yeup Lee, Sang-Gab Kim, Shin-il Choi, Dong-Ju Yang, Hong-Kee Chin, Yu-Gwang Jeong, Ji-Young Park, Dong-Hoon Lee, Byeong-Beom Kim
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Publication number: 20110269253Abstract: A thin film transistor array panel for a flat panel display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting and insulated from the first signal line, a switching element having a first terminal connected to the first signal line, a second terminal connected to the second signal line, and a third terminal, a pixel electrode connected to the third terminal of the switching element, and first and second light blocking members extending parallel to the second signal line, each being disposed on an opposite side of and partially overlapping an respective edge of the second signal line, an interval between the first and second light blocking members being in a range of from more than 1.5 ?m to less than 4 ?m. The array panel prevents light leakage from the display and improves its transmittance, aperture ratio and color reproducibility.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Inventors: Seung-Ha CHOI, Min-Seok Oh, Jeong-Min Park, Doo-Hee Jung, Hi-Kuk Lee, Sang-Gab Kim
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Patent number: 8044405Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.Type: GrantFiled: April 24, 2009Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Kee Chin, Sang-Gab Kim, Woong-Kwon Kim, Yong-Mo Choi, Seung-Ha Choi, Shin-Il Choi, Ho-Jun Lee, Jung-Suk Bang, Yu-Gwang Jeong
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Patent number: 8017459Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.Type: GrantFiled: June 12, 2009Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ju Yang, Yu-Gwang Jeong, Ki-Yeup Lee, Sang-Gab Kim, Yun-Jong Yeo, Shin-Il Choi, Hong-Kee Chin, Seung-Ha Choi, Jung-Suk Bang
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Patent number: 8004636Abstract: A thin film transistor array panel for a flat panel display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting and insulated from the first signal line, a switching element having a first terminal connected to the first signal line, a second terminal connected to the second signal line, and a third terminal, a pixel electrode connected to the third terminal of the switching element, and first and second light blocking members extending parallel to the second signal line, each being disposed on an opposite side of and partially overlapping an respective edge of the second signal line, an interval between the first and second light blocking members being in a range of from more than 1.5 ?m to less than 4 ?m. The array panel prevents light leakage from the display and improves its transmittance, aperture ratio and color reproducibility.Type: GrantFiled: July 22, 2008Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Ha Choi, Min-Seok Oh, Jeong-Min Park, Doo-Hee Jung, Hi-Kuk Lee, Sang-Gab Kim
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Publication number: 20110198603Abstract: Disclosed are a thin film transistor and a method of forming the thin film transistor. The thin film transistor includes a gate electrode, an oxide semiconductor pattern, a first gate insulating layer pattern interposed between the gate electrode and the oxide semiconductor pattern, wherein the first gate insulating layer pattern has an island shape or has two portions of different thicknesses from each other, a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern, wherein the source electrode and the drain electrode are separated from each other, and a first insulating layer pattern placed between the source electrode and drain electrode and the oxide semiconductor pattern, wherein the first insulating layer pattern partially contacts the source electrode and drain electrode and the first gate insulating layer pattern, and wherein the first insulating layer is enclosed by an outer portion.Type: ApplicationFiled: October 12, 2010Publication date: August 18, 2011Inventors: SEUNG-HA CHOI, Kyoung-Jae Chung, Young-Wook Lee
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Publication number: 20110193076Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.Type: ApplicationFiled: December 1, 2010Publication date: August 11, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pil-Sang YUN, Ki-Won KIM, Hye-Young RYU, Woo-Geun LEE, Seung-Ha CHOI, Jae-Hyoung YOUN, Kyoung-Jae CHUNG, Young-Wook LEE, Je-Hun LEE, Kap-Soo YOON, Do-Hyun KIM, Dong-Ju YANG, Young-Joo CHOI
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Patent number: 7982223Abstract: In a display apparatus and a method of manufacturing the display apparatus, a first insulating layer having a trench and a second insulating layer having a via hole corresponding to the trench are formed on an array substrate. After forming a seed layer in the trench, a conductive layer is formed on the seed layer through a plating process, thereby forming the gate line, the gate electrode and the storage line accommodated in the trench and the via hole.Type: GrantFiled: February 17, 2009Date of Patent: July 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Ha Choi, Min-Seok Oh, Sang-Gab Kim, Hong-Kee Chin, Yu-Gwang Jeong
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Publication number: 20110159622Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.Type: ApplicationFiled: March 7, 2011Publication date: June 30, 2011Inventors: Yu-Gwang Jeong, Young-Wook Lee, Sang-Gab Kim, Woo-Geun Lee, Min-Seok Oh, Jang-Soo Kim, Kap-Soo Yoon, Shin-Il Choi, Hong-Kee Chin, Seung-Ha Choi, Seung-Hwan Shim, Sung-Hoon Yang, Ki-Hun Jeong
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Publication number: 20110114940Abstract: A thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; an semiconductive oxide layer disposed on the gate insulating layer; a data line disposed on the semiconductive oxide layer and including a source electrode; a drain electrode facing the source electrode on the semiconductive oxide layer; and a passivation layer disposed on the data line. The semiconductive oxide layer is patterned with chlorine (Cl) containing gas which alters relative atomic concentrations of primary semiconductive characteristic-providing elements of the semiconductive oxide layer at least at a portion where a transistor channel region is defined.Type: ApplicationFiled: June 17, 2010Publication date: May 19, 2011Inventors: Do-Hyun Kim, Kyoung-Jae Chung, Seung-Ha Choi, Dong-Hoon Lee, Chang-Oh Jeong, Suk-Won Jung
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Patent number: 7935580Abstract: A display substrate includes a gate line, a storage capacitor, a source line, a switching element, a pixel electrode, and a color filter. The gate line is formed on a base substrate. The storage capacitor has a storage line substantially parallel to the gate line. The source line crosses the gate line to define a pixel area. The switching element is connected to the gate line and the source line. The pixel electrode contacts the switching element. The color filter pattern is formed between the base substrate and the pixel electrode such that the color filter pattern contracts the base substrate and the pixel electrode. Thus, the color filter pattern is formed on the display substrate using a three-mask process.Type: GrantFiled: September 28, 2007Date of Patent: May 3, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Seok Oh, Shi-Yul Kim, Sang-Gab Kim, Joo-Han Kim, Hong-Kee Chin, Yu-Gwang Jeong, Seung-Ha Choi
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Publication number: 20110097961Abstract: In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.Type: ApplicationFiled: December 29, 2010Publication date: April 28, 2011Inventors: Min-Seok OH, Yang-Ho BAE, Pil-Sang YUN, Byeong-Beom KIM, Seung-Ha CHOI, Sang-Gab KIM, Chang-Ho JEONG, Shin-Il CHOI, Hong-Kee CHIN, Yu-Gwang JEONG, Dong-Ju YANG
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Patent number: 7923732Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.Type: GrantFiled: December 9, 2008Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yu-Gwang Jeong, Young-Wook Lee, Sang-Gab Kim, Woo-Geun Lee, Min-Seok Oh, Jang-Soo Kim, Kap-Soo Yoon, Shin-Il Choi, Hong-Kee Chin, Seung-Ha Choi, Seung-Hwan Shim, Sung-Hoon Yang, Ki-Hun Jeong
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Publication number: 20110062445Abstract: A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask, Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.,Inventors: Min-Seok OH, Bong-Kyu SHIN, Sang-Gab KIM, Eun-Guk LEE, Hong-Kee CHIN, Yu-Gwang JEONG, Seung-Ha CHOI
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Publication number: 20110024752Abstract: A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer.Type: ApplicationFiled: October 8, 2010Publication date: February 3, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shin-Il CHOI, Sang-Gab KIM, Hong-Kee CHIN, Min-Seok OH, Yu-Gwang JEONG, Seung-Ha CHOI
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Patent number: 7868958Abstract: A method for forming a liquid crystal display device includes incremental removal of a gate insulator. After forming a gate line layer, a gate insulator, a semiconductor layer, a data layer and a photoresist layer, a mask is used to define a plurality of regions in the photoresist layer through selective development. The developed portions of the photoresist layer are removed and parts of the underlying layers are etched in a plurality of steps using the photoresist layer as a mask. The gate insulator is partially removed during the etching of the data layer and completely removed during formation of source and drain electrodes.Type: GrantFiled: August 31, 2007Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Ha Choi, Min-Seok Oh, Sang-Gab Kim, Jae-Ho Choi, Yu-Gwang Jeong
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Patent number: 7863065Abstract: A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.Type: GrantFiled: March 7, 2007Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Seok Oh, Bong-Kyu Shin, Sang-Gab Kim, Eun-Guk Lee, Hong-Kee Chin, Yu-Gwang Jeong, Seung-Ha Choi
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Patent number: 7858986Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof. The thin film transistor array panel according to the present invention includes a substrate, a light blocking member formed on the substrate, a gate line disposed on the light blocking member. The gate line and the light blocking member define a closed region A color filter is formed in the closed region and contacts the side surface of the gate line. A gate insulating layer is formed on the gate line and the color filter, a data line and a drain electrode are formed on the gate insulating layer, and a pixel electrode is connected to the drain electrode.Type: GrantFiled: October 1, 2008Date of Patent: December 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Seok Oh, Seung-Ha Choi, Yoon-Ho Kang, Hong-Kee Chin, Yu-Gwang Jeong