Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

Abstract: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

Abstract: An embodiment includes a system comprising: a thin film transistor (TFT) comprising a source, a channel, a drain, and a gate; first, second, and third dielectric portions; wherein (a) a first vertical axis intersects the source, the channel, and the drain; (b) the first dielectric portion surrounds the source in a first plane; (c) the second dielectric portion surrounds the channel in a second plane; (d) the third dielectric surrounds the drain in a third plane; (e) a second vertical axis intersects the first, second, and third dielectric portions; (f) the source includes a first dopant, the first dielectric portion includes the first dopant, the second dielectric portion includes at least one of the first dopant and a second dopant, the drain includes the at least one of the first and second dopants, and the third dielectric portion includes the at least one of the first and second dopants.

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

Abstract: A quick connector assembly configured to, when a coupling case is separated from an outer case, airtightness may be maintained without fully separating the fixing member. The quick connector assembly includes an tubular outer case having a hollow portion, a coupling case inserted into the hollow portion to be connected to the outer case so as to allow fluid flow, an airtightness maintaining member provided inside the hollow portion and coupled to an outer surface of the coupling case to maintain airtightness between the coupling case and the outer case, and a fixing member detachably fitted from an outside of the outer case to fix the coupling case inserted into the hollow portion by elasticity thereof, wherein the fixing member is introduced toward the hollow portion from outside of the outer case to thereby fix an outer surface of the coupling case located inside the hollow portion by compression.

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Abstract: Nanowire transistors including embedded dielectric spacers to separate a gate electrode from source and drain regions of the transistor. Embedded spacers are disposed within interior sidewalls of a passage through which the gate electrode wraps around a semiconductor filament. The presence of these embedded spacers may dramatically reduce fringe capacitance, particularly as the number of wires/ribbons/filaments in the transistor increases and the number of interior gate electrode passages increases. In some advantageous embodiments, embedded dielectric spacers are fabricated by encapsulating external surfaces prior to those surfaces becoming embedded within the transistor.

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.

Abstract: Techniques are disclosed for forming transistors including retracted raised source/drain (S/D) to reduce parasitic capacitance. In some cases, the techniques include forming ledges for S/D epitaxial regrowth on a high-quality crystal nucleation surface. The techniques may also include forming the raised sections of the S/D regions (e.g., the portions adjacent to spacer material between the S/D regions and the gate material) in a manner such that the S/D raised sections are retracted from the gate material. This can be achieved by forming a notch at the interface between a polarization charge inducing layer and an oxide layer using a wet etch process, such that a relatively high-quality surface of the polarization charge inducing layer material is exposed for S/D regrowth. Therefore, the benefits derived from growing the S/D material from a high-quality nucleation surface can be retained while reducing the parasitic overlap capacitance penalty that would otherwise be present.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.