Patents by Inventor Seung-hun Lee

Seung-hun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790133
    Abstract: A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum Seok Park, Sun Jung Kim, Yi Hwan Kim, Pan Kwi Park, Dong Suk Shin, Hyun Kwan Yu, Seung Hun Lee
  • Patent number: 10784562
    Abstract: A wireless communication chip having an internal antenna includes a substrate having first and second mounting regions; a wireless communication module molded on the first mounting region; and an antenna block mounted on the second mounting region to be electrically connected to the wireless communication module, wherein the antenna block includes a first antenna on the substrate; a connection element connected to the first antenna; an insulating layer on the first antenna and the connection element to cover the first antenna and the connection element; and a second antenna on the insulating layer such that a first surface of the second antenna is in contact with the insulating layer, and a second surface, which is a reverse surface of the first surface, is exposed to the outside of the wireless communication chip, wherein the second antenna is electrically connected to the first antenna through the connection element.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 22, 2020
    Assignee: LS MTRON LTD.
    Inventors: Tae Hyung Kim, Seung Hun Lee, Hangnga Nguyen, Seong Soo Han, Young Ho Kim
  • Patent number: 10784379
    Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hoon Kim, Dong Myoung Kim, Dong Suk Shin, Seung Hun Lee, Cho Eun Lee, Hyun Jung Lee, Sung Uk Jang, Edward Nam Kyu Cho, Min-Hee Choi
  • Patent number: 10775699
    Abstract: Disclosed is a negative photoresist composition for a KrF laser, having high resolution and a high aspect ratio and, more particularly, a negative photoresist composition for a KrF laser, which includes a specific additive in order to improve the properties of a conventional negative photoresist, whereby the negative photoresist composition can prevent fine-pattern collapse even using a short-wavelength exposure light source, compared to conventional negative photoresists, and can also exhibit high resolution and a high aspect ratio and is thus suitable for use in semiconductor processing.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: September 15, 2020
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Seung Hun Lee, Seung Hyun Lee, Su Jin Lee, Young Cheol Choi
  • Patent number: 10762935
    Abstract: A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Myung Kyun Kwak, Woongrae Kim, Seung Hun Lee
  • Patent number: 10754724
    Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui Chung Byun, Yoen Hwa Lee, Seung Hun Lee
  • Publication number: 20200266101
    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-yeong JOE, Seok-hoon KIM, Jeong-ho YOO, Seung-hun LEE, Geun-hee JEONG
  • Publication number: 20200259152
    Abstract: A battery module which includes: a battery stack formed by stacking a plurality of battery cells respectively including electrode tabs on each other; and bus bar assemblies located on sides of the battery stack, from which the electrode tabs are drawn out, to electrically connect the plurality of battery cells to each other through a plurality of electrode tabs, wherein each of the bus bar assemblies includes a plurality of openings configured to hold the plurality of electrode tabs, and each of the plurality of openings includes an insertion portion formed by opening one side thereof so that the electrode tab is slidely inserted in a direction perpendicular to a direction in which the electrode tabs are drawn out.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Seung Hun LEE, Tae Gu LEE, Kwan Yong KIM, Kenneth KIM
  • Publication number: 20200259140
    Abstract: A battery module which includes: a battery stack formed by stacking a plurality of battery cells respectively including electrode tabs on each other; a pair of side covers disposed on both sides of the battery stack; a lower cover on which the battery stack is placed so that one side of the plurality of battery cells is in contact therewith; and an upper cover disposed on a side opposite to the lower cover with respect to the battery stack; wherein the pair of side covers and the upper cover are integrally formed, and the lower cover is fastened to at least one of the pair of side covers.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Seung Hun LEE, Yun Joo NOH, Tae Gu LEE
  • Publication number: 20200259155
    Abstract: A battery module which includes: a battery stack formed by stacking a plurality of battery cells respectively including electrode tabs on each other; bus bar assemblies located on both sides of the battery stack, from which the electrode tabs are drawn, to electrically connect the plurality of battery cells to each other through the plurality of electrode tabs; and a sensing module assembly disposed on one side of the battery stack, from which the electrode tab is not drawn out, to electrically connect the bus bar assemblies on both sides of the battery stack.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Seung Hun LEE, Yun Joo NOH, Tae Gu LEE
  • Patent number: 10734042
    Abstract: A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Myung Kyun Kwak, Seung Hun Lee
  • Patent number: 10725495
    Abstract: A power gating system includes a logic circuit region including at least one logic gate configured to receive a first gating clock signal. The power gating system also includes a power gating control circuit configured to generate the first gating clock signal which is controlled to start transition after stabilization of an internal power voltage according to a chip select signal, a command/address signal, and an external clock signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Woongrae Kim, Seung Hun Lee
  • Patent number: 10717878
    Abstract: The present invention relates to an anti-reflective coating solution composition and an anti-reflective coating film using the same. More particularly, an anti-reflective coating solution composition is provided, which has a low refractive index to thus improve transmittance and can also increase abrasion resistance to thus maintain an anti-reflective effect for a long period of time, whereby an anti-reflective coating film for improving solar cell module efficiency can be formed, and thus can be applied not only to a solar cell module glass but also to glass in a variety of fields.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: July 21, 2020
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Seung Hun Lee, Seung Hyun Lee, Gyeong Guk Ham
  • Patent number: 10714387
    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-yeong Joe, Seok-hoon Kim, Jeong-ho Yoo, Seung-hun Lee, Geun-hee Jeong
  • Patent number: 10693017
    Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hun Lee, Dong Woo Kim, Dong Chan Suh, Sun Jung Kim
  • Publication number: 20200190423
    Abstract: Disclosed is a cutting oil composition, which is vastly superior in view of layer separation, dispersibility, viscosity, ingot-cleaning time after sawing, and wafer warpage after sawing, compared to conventional cutting oil compositions, and which includes mineral oil that is highly hydrogenated, as represented by Chemical Formulas 1 to 3, bentonite clay as a thickener, and glycerol trioleate as a dispersant. A cutting method using the cutting oil composition is also provided.
    Type: Application
    Filed: May 31, 2018
    Publication date: June 18, 2020
    Inventors: Seung Hun LEE, Seung Hyun LEE, Seong Hwan KIM, Gyeong Guk HAM
  • Publication number: 20200183284
    Abstract: The present invention relates to a method of reducing the LWR (Line Width Roughness) of a photoresist pattern using a negative tone photoresist during the fabrication of a semiconductor, and more specifically to a composition capable of reducing LWR in order to ensure a higher pattern CDU after a negative tone development process, and a processing method using the composition, thus reducing the LWR, thereby providing better CDU than existing methods.
    Type: Application
    Filed: April 26, 2017
    Publication date: June 11, 2020
    Inventors: Su Jin LEE, Gi Hong KIM, Seung Hun LEE, Seung Hyun LEE
  • Publication number: 20200185539
    Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Seung Hun LEE, Dong Woo KIM, Dong Chan SUH, Sun Jung KIM
  • Publication number: 20200173086
    Abstract: A washing machine including a rotating tub and a motor applying a driving force to the rotating tub. The washing machine configured to generate a starting current to be applied to the motor when it is a start time of the motor, accelerate the speed of the motor stepwise while the starting current is applied to the motor, check a current of a torque component when it is determined as a deceleration time or a stop time, and apply a current of a magnetic flux component greater than the magnitude of the current of the checked torque component to the motor.
    Type: Application
    Filed: November 29, 2019
    Publication date: June 4, 2020
    Inventors: Seung Hun LEE, Jun Hyun PARK
  • Publication number: 20200176035
    Abstract: A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.
    Type: Application
    Filed: July 9, 2019
    Publication date: June 4, 2020
    Applicant: SK hynix Inc.
    Inventors: Woongrae KIM, Myung Kyun KWAK, Seung Hun LEE