Patents by Inventor Seung-hun Lee

Seung-hun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210367036
    Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.
    Type: Application
    Filed: December 20, 2020
    Publication date: November 25, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: JINBUM KIM, DAHYE KIM, SEOKHOON KIM, JAEMUN KIM, ILGYOU SHIN, Haejun YU, KYUNGIN CHOI, KIHYUN HWANG, SANGMOON LEE, SEUNG HUN LEE, KEUN HWI CHO
  • Publication number: 20210350839
    Abstract: An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.
    Type: Application
    Filed: June 22, 2021
    Publication date: November 11, 2021
    Applicant: SK hynix Inc.
    Inventors: Woongrae KIM, Kyung Mook KIM, Seung Hun LEE, Da In IM
  • Patent number: 11169444
    Abstract: The present invention relates to a method of reducing the LWR (Line Width Roughness) of a photoresist pattern using a negative tone photoresist during the fabrication of a semiconductor, and more specifically to a composition capable of reducing LWR in order to ensure a higher pattern CDU after a negative tone development process, and a processing method using the composition, thus reducing the LWR, thereby providing better CDU than existing methods.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: November 9, 2021
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Su Jin Lee, Gi Hong Kim, Seung Hun Lee, Seung Hyun Lee
  • Patent number: 11171135
    Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyojin Kim, Jihye Lee, Sangmoon Lee, Seung Hun Lee
  • Patent number: 11169442
    Abstract: An extreme ultraviolet (EUV) developer composition for use in manufacturing a semiconductor is provided. More particularly an EUV developer composition for forming a fine pattern is provided, which is capable of forming a more uniform pattern and lowering EOP in a development process, the EUV developer composition including a water-soluble polymer represented by Chemical Formula 1, a nonionic surfactant represented by Chemical Formula 2, and an alkali compound.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: November 9, 2021
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Su Jin Lee, Gi Hong Kim, Seung Hun Lee, Seung Hyun Lee
  • Publication number: 20210343841
    Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.
    Type: Application
    Filed: November 3, 2020
    Publication date: November 4, 2021
    Inventors: ILGYOU SHIN, MINYI KIM, MYUNG GIL KANG, JINBUM KIM, SEUNG HUN LEE, KEUN HWI CHO
  • Publication number: 20210333709
    Abstract: Proposed are an organic-inorganic hybrid photoresist processing solution composition for use in a thin film formation process, a development process, and a stripping process of an organic-inorganic hybrid photoresist, and a processing method using the same. The processing solution composition includes a compound of Chemical Formula 1 and a ketone, an ester, an ether, an additive or a mixture thereof, and is superior in processing of organic materials and ability to adsorb inorganic materials, thereby minimizing the remaining inorganic material content, ultimately preventing processing defects from occurring.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 28, 2021
    Inventors: Su Jin LEE, Seung Hun LEE, Seung Hyun LEE
  • Patent number: 11145723
    Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seojin Jeong, Jinyeong Joe, Seokhoon Kim, Jeongho Yoo, Seung Hun Lee, Sihyung Lee
  • Patent number: 11145720
    Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cho-eun Lee, Seok-hoon Kim, Sang-gil Lee, Edward Namkyu Cho, Min-hee Choi, Seung-hun Lee
  • Publication number: 20210305354
    Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Kyoung Seok SON, Myoung Hwa KIM, Jay Bum KIM, Seung Jun LEE, Seung Hun LEE, Jun Hyung LIM
  • Patent number: 11114521
    Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 7, 2021
    Inventors: Kyoung Seok Son, Myoung Hwa Kim, Jay Bum Kim, Seung Jun Lee, Seung Hun Lee, Jun Hyung Lim
  • Publication number: 20210234050
    Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: Seung Hun LEE, Dong Woo KIM, Dong Chan SUH, Sun Jung KIM
  • Publication number: 20210220447
    Abstract: The present disclosure relates to a method for inhibiting a STAT3 activity, and a method for treating inflammatory bowel disease (IBD).
    Type: Application
    Filed: January 21, 2021
    Publication date: July 22, 2021
    Applicant: CUROGEN TECHNOLOGY CO., LTD.
    Inventors: Mi-La CHO, Sung-Hwan Park, Seung-Ki Kwok, Jong-Young Choi, Seung-Hun Lee, Hyeon-Beom Seo, Young-Mee Moon, Jin-Sil Park, Min-Jung Park, Jin-Kwan Lee, Chang Woo Lee
  • Publication number: 20210216013
    Abstract: Proposed is a photoresist composition for a KrF light source, which exhibits a vertical profile compared to conventional KrF positive photoresists by adding a resin capable of increasing transmittance in order to form a semiconductor pattern, particularly a chemically amplified positive photoresist composition for improving a pattern profile, which includes, based on the total weight of the composition, 5 to 60 wt % of a polymer resin, 0.1 to 10 wt % of a transmittance-increasing resin additive represented by Chemical Formula 1, 0.05 to 10 wt % of a photoacid generator, 0.01 to 5 wt % of an acid diffusion inhibitor, and the remainder of a solvent, thus making it possible to provide a composition exhibiting a vertical profile, enhanced sensitivity and a superior processing margin compared to conventional positive photoresists.
    Type: Application
    Filed: May 22, 2019
    Publication date: July 15, 2021
    Inventors: Su Jin LEE, Young Cheol CHOI, Seung Hun LEE, Seung Hyun LEE
  • Publication number: 20210217860
    Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 15, 2021
    Inventors: Ryong HA, Dongwoo KIM, Gyeom KIM, Yong Seung KIM, Pankwi PARK, Seung Hun LEE
  • Publication number: 20210214649
    Abstract: A processing solution composition for reducing collapse of a polyhydroxystyrene-containing photoresist pattern defined by an extreme-ultraviolet exposure source and a method of forming a pattern using the same are proposed. The processing solution composition includes 0.0001 to 1 wt % of a nonionic surfactant having an HLB (Hydrophilic-Lipophilic Balance) value of 9 to 16, 0.0001 to 1 wt % of an alkaline material selected from the group consisting of tetraethylammonium hydroxide, tetrapropylammonium hydroxide, tetrabutylammonium hydroxide, and mixtures thereof, and 98 to 99.9998 wt % of water, and is effective at reducing the collapse of a polyhydroxystyrene-containing photoresist pattern defined by an extreme-ultraviolet exposure source.
    Type: Application
    Filed: May 22, 2019
    Publication date: July 15, 2021
    Inventors: Su Jin LEE, Seung Hun LEE, Seung Hyun LEE
  • Publication number: 20210193516
    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 24, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-yeong JOE, Seok-hoon KIM, Jeong-ho YOO, Seung-hun LEE, Geun-hee JEONG
  • Publication number: 20210180231
    Abstract: Provided is a washing apparatus and a method of controlling the same. The washing apparatus includes a washing tub; and a controller configured to determine whether laundry put into the washing tub is wet laundry or dry laundry, and to determine a weight of the laundry in the washing tub through a detection of wet laundry weight or a detection of dry laundry weight, based on a result of the determination. The washing apparatus includes a washing tub; and a controller configured to detect a water level of washing water in the washing tub, configured to perform at least one of detecting a weight of wet laundry weight and dry laundry according to the water level, and configured to allow washing to be performed according to at least one result of the detection of the wet laundry weight and the dry laundry weight.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 17, 2021
    Inventors: Hyun Oh Kim, Seung Hun Lee, Jun Hyun Park, Sung Mo Lee, So Dam Han
  • Patent number: 11036134
    Abstract: Provided is a hard mask composition having high etching resistance suitable for use in a semiconductor lithography process, and particularly to a spin-on hard mask composition including a dibenzo carbazole polymer and to a patterning method of forming a hard mask layer by applying the composition on an etching layer through spin coating and performing a baking process. The hard mask according to the present invention has effects of exhibiting high solubility and superior mechanical properties, as well as high etching resistance to withstand multiple etching processes.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 15, 2021
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Gi Hong Kim, Su Jin Lee, Seung Hyun Lee, Seung Hun Lee
  • Publication number: 20210159246
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 27, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung Il KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI