Patents by Inventor Seung-Hun Shin
Seung-Hun Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190189668Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: BYUNG-JUN PARK, CHANG-ROK MOON, SEUNG-HUN SHIN, SEONG-HO OH, TAE-SEOK OH, JUNE-TAEG LEE
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Publication number: 20190148439Abstract: An image sensor includes a semiconductor substrate including a pixel region and a pad region, a plurality of photoelectric conversion regions in the pixel region, an interconnect structure on a front surface of the semiconductor substrate, a pad structure in the pad region and on a rear surface of the semiconductor substrate, a through via structure in the pad region and electrically connected to the interconnect structure through the semiconductor substrate, and an isolation structure at least partially extending through the pad region of the semiconductor substrate from the rear surface of the semiconductor substrate. The isolation structure surrounds the pad structure and the through via structure in a plane extending parallel to the rear surface of the semiconductor substrate.Type: ApplicationFiled: August 22, 2018Publication date: May 16, 2019Applicant: Samsung Electronics Co., ltd.Inventors: Seung-hun SHIN, Duk-seo PARK
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Patent number: 10265038Abstract: The present invention relates to an X-ray photographing device and, more specifically, to an X-ray photographing device comprising a variable type arm which can irradiate, without limitation of location or direction, X-rays to a subject using the variable type arm of which the length and rotation angle of joints, etc. are variable.Type: GrantFiled: January 23, 2015Date of Patent: April 23, 2019Assignees: VATECH Co., Ltd., VATECH EWOO Holdings Co., Ltd.Inventors: Tae Woo Kim, Seung Hun Shin, Keong Tae Yeom, Byung Jik Lim, Jin Pyo Chun, Sung Il Choi
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Patent number: 10229949Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.Type: GrantFiled: June 16, 2017Date of Patent: March 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
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Publication number: 20190058814Abstract: An electronic device is provided. The electronic device includes a housing including a front plate, a back plate, and a side member surrounding a space between the front plate and the back plate. The side member includes a plurality of non-conductive portions and a conductive portion. The electronic device also includes a display module, and at least one wireless communication circuit. The electronic device also includes a printed circuit board (PCB). The camera assembly is exposed through a portion of the back plate. The camera assembly includes an image sensor mounted on the PCB, and a plurality of lenses. The camera assembly also includes a barrel that surrounds the plurality of lenses, and a camera bracket that surrounds at least part of the barrel. The camera assembly also includes a metal case that surrounds at least part of the camera assembly, and a shielding structure.Type: ApplicationFiled: August 2, 2018Publication date: February 21, 2019Inventors: Hyun-Tae JUNG, Seung-Hun SHIN, Chang-Ho HWANG, Min-Soo KIM, Sang-Tae LEE, Ji-Hyuk JANG, Jin-Wan AN
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Patent number: 9825081Abstract: A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate.Type: GrantFiled: August 5, 2016Date of Patent: November 21, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taeseok Oh, Junetaeg Lee, Seung-Hun Shin, Jaesang Yoo
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Publication number: 20170287967Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: BYUNG-JUN PARK, CHANG-ROK MOON, SEUNG-HUN SHIN, SEONG-HO OH, TAE-SEOK OH, JUNE-TAEG LEE
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Patent number: 9728572Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.Type: GrantFiled: December 5, 2014Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
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Patent number: 9608026Abstract: Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.Type: GrantFiled: June 1, 2015Date of Patent: March 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Park, Seung-Hun Shin
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Publication number: 20170040374Abstract: A semiconductor device includes a substrate, a circuit layer formed on a first surface of the substrate and including a via pad and an interlayer insulating layer covering the via pad, a via structure configured to fully pass through the substrate, partially pass through the interlayer insulating layer and be in contact with the via pad, a via isolation insulating layer configured to pass through the substrate and be spaced apart from outer side surfaces of the via structure in a horizontal direction and a pad structure buried in the substrate and exposed on a second surface of the substrate opposite the first surface of the substrate.Type: ApplicationFiled: August 5, 2016Publication date: February 9, 2017Inventors: Taeseok OH, Junetaeg LEE, Seung-Hun SHIN, Jaesang YOO
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Publication number: 20160365374Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.Type: ApplicationFiled: August 29, 2016Publication date: December 15, 2016Inventors: Byung-Jun PARK, Seung-Hun SHIN, Chang-Rok MOON, Tae-Seok OH, June-Taeg LEE
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Publication number: 20160338657Abstract: The present invention relates to an X-ray photographing device and, more specifically, to an X-ray photographing device comprising a variable type arm which can irradiate, without limitation of location or direction, X-rays to a subject using the variable type arm of which the length and rotation angle of joints, etc. are variable.Type: ApplicationFiled: January 23, 2015Publication date: November 24, 2016Applicants: VATECH Co., Ltd., VATECH EWOO Holdings Co., Ltd.Inventors: Tae Woo KIM, Seung Hun SHIN, Keong Tae YEOM, Byung Jik LIM, Jin Pyo CHUN, Sung Il CHOI
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Patent number: 9455284Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.Type: GrantFiled: January 22, 2015Date of Patent: September 27, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-Jun Park, Seung-Hun Shin, Chang-Rok Moon, Tae-Seok Oh, June-Taeg Lee
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Patent number: 9443892Abstract: An image sensor includes a substrate having a first surface opposing a second surface and a plurality of pixel regions. A photoelectric converter is included in each of the pixel regions, and a gate electrode is formed on the photoelectric converter. Also, a pixel isolation region isolates adjacent pixel regions. The pixel isolation region includes a first isolation layer coupled to a channel stop region. The channel stop region may include an impurity-doped region.Type: GrantFiled: February 18, 2014Date of Patent: September 13, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: June-mo Koo, Sang-Hoon Kim, Seung-Hun Shin, Jongcheol Shin
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Publication number: 20150311241Abstract: A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.Type: ApplicationFiled: January 22, 2015Publication date: October 29, 2015Inventors: Byung-Jun PARK, Seung-Hun SHIN, Chang-Rok MOON, Tae-Seok OH, June-Taeg LEE
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Patent number: 9165974Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.Type: GrantFiled: September 15, 2014Date of Patent: October 20, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-kwan Kim, Doo-won Kwon, Jeong-ki Kim, Wook-hwan Kim, Byung-jun Park, Seung-hun Shin, June-taeg Lee, Ha-kyu Choi, Tae-seok Oh
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Publication number: 20150263060Abstract: Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Inventors: Byung-Jun PARK, Seung-Hun Shin
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Publication number: 20150221695Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.Type: ApplicationFiled: December 5, 2014Publication date: August 6, 2015Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
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Patent number: 9048354Abstract: Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.Type: GrantFiled: March 14, 2013Date of Patent: June 2, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Jun Park, Seung-Hun Shin
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Publication number: 20150076649Abstract: An electronic device may include a first semiconductor layer, a first electrode layer on the semiconductor layer, an adhesive insulating layer on the first electrode layer, a second electrode layer on the adhesive insulating layer, a second semiconductor layer. The first electrode layer may include a first plurality of electrodes, the first electrode layer may be between the adhesive insulating layer and the first semiconductor layer, and the adhesive insulating layer may include at least one of SiOCN, SiBN, and/or BN. The second electrode layer may include a second plurality of electrodes, the adhesive insulating layer may be between the first and second electrode layers, and the second electrode layer may be between the adhesive insulating layer and the second semiconductor layer.Type: ApplicationFiled: September 15, 2014Publication date: March 19, 2015Inventors: Sung-kwan KIM, Doo-Won Kwon, Jeong-ki Kim, Wook-hwan Kim, Byung-jun Park, Seung-hun Shin, June-taeg Lee, Ha-kyu Choi, Tae-Seok Oh