Abstract: A semiconductor substrate includes a photodiode on a support substrate. An insulating layer is provided between the support substrate and the semiconductor substrate. A first conductive pattern is provided in the insulating layer. A first through electrode penetrates the support substrate to be in contact with the first conductive pattern.

Abstract: An image sensor includes a substrate having a first surface opposing a second surface and a plurality of pixel regions. A photoelectric converter is included in each of the pixel regions, and a gate electrode is formed on the photoelectric converter. Also, a pixel isolation region isolates adjacent pixel regions. The pixel isolation region includes a first isolation layer coupled to a channel stop region. The channel stop region may include an impurity-doped region.

Abstract: Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.

Abstract: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

Abstract: An image sensor and a method of forming the same, where the image sensor may include a substrate including a pixel region and a pad region, a through via configured to penetrate the substrate in the pad region, a plurality of unit pixels in the pixel region, and a light shielding pattern between the plurality of unit pixels. The through via and the light shielding pattern include a same material.

Abstract: A semiconductor substrate includes a photodiode on a support substrate. An insulating layer is provided between the support substrate and the semiconductor substrate. A first conductive pattern is provided in the insulating layer. A first through electrode penetrates the support substrate to be in contact with the first conductive pattern.

Abstract: In a method of manufacturing a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), an epitaxial layer may be formed on a first substrate including a chip area and a scribe lane area. A first impurity layer may be formed adjacent to the first substrate by implanting first impurities into the epitaxial layer. A photodiode may be formed in the epitaxial layer on the chip area. A circuit element electrically connected to the photodiode may be formed on the epitaxial layer. A protective layer protecting the circuit element may be formed on the epitaxial layer. A second substrate may be attached onto the protective layer. The first substrate may be removed to expose the epitaxial layer. A color filter layer may be formed on the exposed epitaxial layer using the first impurity layer as an alignment key. A microlens may be formed over the color filter layer.

Abstract: For fabricating an image sensor, an isolation structure is formed to define a first active region of a semiconductor substrate. A first transistor and a second transistor of a unit pixel are formed in the first active region. In addition, a threshold voltage lowering region is formed in a portion of the semiconductor substrate near a portion of the isolation structure abutting the second transistor in the first active region. The threshold voltage lowering region causes the second transistor to have a respective threshold voltage magnitude that is lower than for the first transistor. The threshold voltage lowering region is formed simultaneously with a passivation region in a second active region having a photodiode formed therein.

Abstract: An image device and a method of fabricating the image device include a substrate pattern formed to define an opening and to include a portion of a photodiode for receiving light. Stacked metal interconnection patterns and an interlayer dielectric layer are formed beneath the substrate pattern. A height of the opening equals a height of the substrate pattern, such that an exposed portion of a top surface of the interlayer dielectric layer provides a bottom surface of the opening. An external connection electrode is positioned on the bottom surface of the opening.

Abstract: For fabricating an image sensor, an isolation structure is formed to define a first active region of a semiconductor substrate. A first transistor and a second transistor of a unit pixel are formed in the first active region. In addition, a threshold voltage lowering region is formed in a portion of the semiconductor substrate near a portion of the isolation structure abutting the second transistor in the first active region. The threshold voltage lowering region causes the second transistor to have a respective threshold voltage magnitude that is lower than for the first transistor. The threshold voltage lowering region is formed simultaneously with a passivation region in a second active region having a photodiode formed therein.

Abstract: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

Abstract: In a method of manufacturing a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), an epitaxial layer may be formed on a first substrate including a chip area and a scribe lane area. A first impurity layer may be formed adjacent to the first substrate by implanting first impurities into the epitaxial layer. A photodiode may be formed in the epitaxial layer on the chip area. A circuit element electrically connected to the photodiode may be formed on the epitaxial layer. A protective layer protecting the circuit element may be formed on the epitaxial layer. A second substrate may be attached onto the protective layer. The first substrate may be removed to expose the epitaxial layer. A color filter layer may be formed on the exposed epitaxial layer using the first impurity layer as an alignment key. A microlens may be formed over the color filter layer.

Abstract: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

Abstract: An image device and a method of fabricating the image device include a substrate pattern formed to define an opening and to include a portion of a photodiode for receiving light. Stacked metal interconnection patterns and an interlayer dielectric layer are formed beneath the substrate pattern. A height of the opening equals a height of the substrate pattern, such that an exposed portion of a top surface of the interlayer dielectric layer provides a bottom surface of the opening. An external connection electrode is positioned on the bottom surface of the opening.

Abstract: An image sensor and a method of manufacturing the same are disclosed. An image sensor is formed by forming a photoelectric transformation element at a front surface of a semiconductor substrate in an active pixel sensor region and in an optical black region of the semiconductor substrate, subjecting a surface of the semiconductor substrate opposite the front surface to a removal process to create a back surface of the semiconductor substrate, and forming a light blocking film pattern on the back surface in the optical black region. The light blocking film pattern includes an organic material.

Abstract: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.