Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.

Abstract: Provided is a method of manufacturing a light-emitting element, the method including positioning a substrate, forming a first separation layer, which includes a first sacrificial layer, an etching control layer on the first sacrificial layer, and a second sacrificial layer on the etching control layer, on the substrate, forming at least one first light-emitting element on the first separation layer, and separating the first light-emitting element from the substrate.

Abstract: A capsulorhexis device is inserted into an incision site of a cornea to make an incision in an anterior capsule surrounding a crystalline lens. The capsulorhexis device includes a loop having elasticity and conductivity; a moving member having one end fixed and coupled to the loop; an insertion guide configured so that, while the incision is being made in the crystalline lens capsule, a front end thereof is inserted into the incision site of the cornea; and a housing having one end coupled to a rear end of the insertion guide, wherein the loop is housed in the housing and, to make the incision in the crystalline lens capsule, slides in the housing together with the moving member to pass through the insertion guide and be deployed into an anterior chamber of the eye.

Abstract: Provided is a ceiling storage system capable of correcting a working position and constantly checking stability of a structure by detecting an amount of change in a facility. According to the ceiling storage system, a transport vehicle moves to an upper portion of a first storage area of a plurality of storage areas in a state of gripping an article, and the transport vehicle measures a first distance value between the transport vehicle and the first storage area using a distance sensor and measures a relative position value between the transport vehicle and the first storage area using a vision sensor, before unloading the article from the first storage area.

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2?m<PPG and PPG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch PPG>m*P.

Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

Abstract: A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h1 and a first number of Mx layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h2 and a second number of Mx layer tracks that extend unidirectionally in the second direction, where h2>h1 and the second number of Mx layer tracks is greater than the first number of Mx layer tracks. At least one of a height ratio hR=h2/h1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.

Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

Abstract: A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2?m<PPG and PPG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell.

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.

Abstract: A hybrid fin flip flop circuit may comprise a mixture of 1-fin transistors and multi-fin transistors. In one example, a flip flop circuit may comprise 1-fin transistors in at least one of the critical paths of the flip flop circuit such as the drive circuit, the input circuit, or the output circuit. In one example, a flip flop circuit may include: an input circuit; a clock driver circuit; an output circuit; and a latch circuit; wherein one of the input circuit, the clock driver circuit, or the output circuit comprises a multi-fin transistor and the latch circuit comprises a plurality of 1-fin transistors.