Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.

Abstract: A perpendicular magnetic tunnel junction may include a free layer, a reference layer, and a barrier layer. The barrier layer may be arranged between the free layer and the reference layer. The barrier layer may include a first interface and a second interface. The first interface may face the free layer, and a second interface may face the reference layer. The first interface may not physically correlate with the second interface.

Abstract: In certain aspects, a system comprises a power collapsible logic block, a plurality of retention flip-flops coupled to the power collapsible logic blocks, wherein the plurality of retention flip-flops includes a group of master-slave flip-flops and a group of balloon flip-flops, and a power controller configured to retain states of the group of balloon flip-flops and states of the group of master-slave flip-flops in a first sleep state and to retain the states of the group of balloon flip-flops but not states of the group of master-slave flip-flops in a deep sleep state.

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

Abstract: Transistor noise tolerant, non-volatile (NV) resistance element-based static random access memory (SRAM) physically unclonable function (PUF) circuits and related systems and methods. In exemplary aspects, a transistor and its complementary transistor, such as a pull-up transistor and complement pull-down transistor or pull-down transistor and complement pull-up transistor, of the PUF circuit are replaced with passive NV resistance elements coupled to the respective output node and complement output node to enhance imbalance between cross-coupled transistors of the PUF circuit for improved PUF output reproducibility. The added passive NV resistance elements replacing pull-up or pull-down transistors in the PUF circuit reduces or eliminates transistor noise that would otherwise occur if the replaced transistors were present in the PUF circuit as a result of changes in temperature, voltage variations, and aging effect.

Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

Abstract: Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.

Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.

Abstract: In certain aspects, an apparatus comprises a plurality of PUF cells. Each PUF cell comprises a first transistor in series with a first loading resistive component and coupled to a common cross-coupled node and cross-coupled to a complementary common cross-coupled node, a second transistor in series with a second loading resistive component and coupled to the complementary common cross-coupled node and cross-coupled to the common cross-coupled node, a first pass-gate and a second pass-gate coupled to a bit line and the complementary bit line, respectively. The apparatus further comprises an auxiliary peripheral circuit coupled to the bit line, the complementary bit line, the common cross-coupled node, and the complementary common cross-coupled node. During activation, the selected PUF cell, together with the auxiliary peripheral circuit, forms a cross-coupled inverter pair and outputs a physical unclonable function value.

Abstract: Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.

Abstract: Exemplary features pertain to secure communications using Physical Unclonable Function (PUF) devices. Segments of a message to be encrypted are sequentially applied to a PUF device as a series of challenges to obtain a series of responses for generating a sequence of encryption keys, whereby a previous segment of the message is used to obtain a key for encrypting a subsequent segment of the message. The encrypted message is sent to a separate (receiving) device that employs a logical copy of the PUF device for decrypting the message. The logical copy of the PUF may be a lookup table or the like that maps all permissible challenges to corresponding responses for the PUF and may be generated in advance and stored in memory of the receiving device. The data to be encrypted may be further encoded to more fully exercise the PUF to enhance security. Decryption operations are also described.

Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.

Abstract: Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

Abstract: Physically unclonable function (PUF) circuits employing multiple PUF memories to decouple a PUF challenge input from a PUF response output for enhanced security. The PUF circuit includes a PUF challenge memory and a PUF response memory. In response to a read operation, the PUF challenge memory uses a received PUF challenge input data word to address PUF challenge memory arrays therein to generate a plurality of intermediate PUF challenge output data words. The PUF response memory is configured to generate a second, final PUF response output data word in response to intermediate PUF challenge output data words. In this manner, it is more difficult to learn the challenge-response behavior of the PUF circuit, because the PUF challenge input data word does not directly address a memory array that stores memory states representing final logic values in the PUF response output data word.

Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

Abstract: A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.

Abstract: Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells enhanced by stress for increased PUF output reproducibility. Stress voltage applied to SRAM bit cells enhances their skew so that the SRAM bit cells output their preferred initial state in subsequent PUF read operations regardless of process variation and other external environmental variations, such as temperature. The application of stress voltage on the SRAM bit cells in a PUF memory array takes advantage of the recognition of aging effect in transistors, where turning transistors on and off over time can increase threshold voltage resulting in lower drive current. Stress voltage can be applied to the SRAM bit cells to bias their threshold voltage to simulate this aging effect to enhance mismatch between transistors in the SRAM bit cell to more fully skew the SRAM bit cells for increased PUF output reproducibility with less susceptible to noise.

Abstract: Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory. The MRAM includes an MRAM array comprising an MRAM data array of data MRAM bit cells and an MRAM PUF array comprising PUF MRAM bit cells to form an integrated MRAM PUF array in the MRAM array. A resistance sensed from the PUF MRAM bit cells is compared to a reference resistance between the reference MRAM bit cells in the accessed MRAM bit cell row circuit in response to a read operation to cancel or mitigate the effect of process variations on MRAM bit cell resistance. The difference in sensed resistance and reference resistance is used to generate a random PUF output. By integrating the MRAM PUF array into an MRAM array containing an MRAM data array, access circuitry can be shared to control access to the MRAM data array and MRAM PUF, thus saving memory area.