Abstract: Disclosed herein are an apparatus and method for a multi-cloud service platform. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program may receive a service request from a user client device, generate a multi-cloud infrastructure service using multiple clouds in response to the service request, make the multiple clouds interoperate with mufti-cloud infrastructure in order to provide the multi-cloud infrastructure service, and generate a multi-cloud application runtime environment corresponding to the multi-cloud infrastructure service.

Abstract: A refrigerant cycle pressure control system includes: a heat exchanger cooling boil-off gas received from a storage tank; a refrigerant cycle including a refrigerant circulation line, a refrigerant compressor, and an expander; an inventory tank storing the refrigerant to be charged to the refrigerant cycle; a refrigerant supply line connecting the inventory tank to an upstream side of the refrigerant compressor to replenish the refrigerant cycle with the refrigerant; a refrigerant discharge line connecting a downstream side of the refrigerant compressor to the inventory tank to discharge the refrigerant from the refrigerant cycle to the inventory tank; and a pressure regulation line branched off of the refrigerant discharge line. The refrigerant cycle is depressurized by discharging the refrigerant from the refrigerant cycle through the refrigerant discharge line or the pressure regulation line.

Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.

Abstract: A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.

Abstract: A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.

Abstract: A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract: A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

Abstract: A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.

Abstract: A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other.

Abstract: A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.

Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.